Multi-Write Avoidance Encoding for Semiconductor Memory Cells

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor memory technologies, such as write-once memory and one-time programmable memory, face limitations in multiple state changes, leading to issues like bit line disturbances and noise due to attempted re-writes of previously written cells, and progressive weakening of cells with each state change in flash memory.

Innovation Solution

Implementing multi-write avoidance encoding using delta encoding, where only cells requiring a state change from 0 to 1 are written, avoiding re-write of single-bit storage cells already set to 1 and cells set to 0, by using look-up tables or pattern generators to generate and validate code words that meet the multi-write avoidance requirement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MCRA encoding is used to enable multiple data word writes to a target memory location, then the number of times a memory location can be written increases, but individual storage cells are still subjected to multiple state changes which causes bit line disturbances and noise

Engineering Contradiction:
Improvenumber of times memory location can be writtenVSAvoidbit line stability and noise level
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the code word into individual bit positions and tracks the write status of each storage cell separately. By dividing the code word into discrete segments (bit positions), the system can identify and prevent re-writes to specific cells that have already been written, thereby eliminating bit line disturbances while still allowing multiple logical writes to the memory location.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary tracking of which storage cells have been written before attempting a write operation. By maintaining write status information in advance and checking it before each write attempt, the system prevents harmful re-writes to cells that have already been programmed, thus avoiding bit line noise and instability issues.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If multiple state changes are attempted on storage cells, then more data can be written to the same memory location, but the cells become progressively weaker and more unstable

Engineering Contradiction:
Improvedata write flexibilityVSAvoidcell stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the write status of each storage cell is tracked and used to control subsequent write operations. The system receives feedback about which cells have been written and uses this information to prevent further write attempts to those cells, thereby maintaining cell stability while still enabling versatile data storage through alternative code word selections.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If EEPROM cells are re-programmed multiple times, then data can be updated, but the process requires UV light exposure and bulk erasure which is time-consuming and complex

Engineering Contradiction:
Improvedata update capabilityVSAvoiderase and reprogram time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent extracts only the necessary write operations from the bulk erasure process by identifying specific storage cells that need to be written and preventing re-writes to already-programmed cells. This selective approach eliminates the need for time-consuming UV light exposure and bulk erasure operations, allowing rapid data updates without the overhead of traditional EEPROM re-programming procedures.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9715943B2Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods
Publication Date: 2017.07.25 TEXAS INSTRUMENTS INC
  • US9715943B2 patent drawing
  • US9715943B2 patent drawing
  • US9715943B2 patent drawing

AI summary

Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.