N-channel P-well EEPROM Segmentation for Bit Disturbance Reduction
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Solution Overview
Problem
Existing N-channel EEPROM technologies face challenges in minimizing bit disturbances and voltage withstand requirements during programming and erasing, leading to increased silicon area overhead and vulnerability to electrical stress due to high erase/write voltages, especially in smaller geometry circuits.
Innovation Solution
The solution involves creating an N-channel/P-well electrically erasable programmable read-only memory array with independently programmable memory segments by fabricating multiple P-wells within a deep N-well or segmenting a P-well using p-n junction or dielectric isolation, allowing for reduced voltage stress through specific biasing of memory cell and support circuitry elements during write and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If N-channel EEPROM cells are programmed and erased using conventional methods, then programming and erasing operations can be performed, but bit disturbances increase and voltage withstand requirements increase
Solution Approach 1:
The patent applies parameter changes by carefully controlling voltage levels and timing sequences during programming and erasing operations. Specific voltage magnitudes and polarity combinations are used to minimize bit disturbances while reducing voltage stress on memory cells and supporting circuitry.
Solution Approach 2:
The memory array is divided into independently programmable segments using P-well segmentation. This allows selective programming of only the required memory segments rather than entire rows, reducing the number of bits subjected to programming voltage stress and thereby minimizing bit disturbances.
2Ease of operation
If byte select transistors are added to enable byte-level programming, then selective byte programming is achieved, but silicon area overhead increases
Solution Approach 1:
The patent segments the P-well into multiple independently controllable regions, each corresponding to a byte or group of bytes. This segmentation enables byte-selectable programming without requiring additional byte select transistors, as the P-well segmentation itself provides the selection mechanism.
Solution Approach 2:
The P-well structure serves multiple functions: it acts as the substrate for N-channel devices, provides voltage isolation between memory segments, and enables byte-selectable programming through independent voltage control of segmented regions. This multi-functionality eliminates the need for separate byte select transistors.
3Productivity
If smaller geometry transistors are used to increase integration density, then more memory cells fit in the same area, but voltage breakdown becomes more problematic
Solution Approach 1:
The P-well is segmented into electrically isolated sub-regions that can be independently biased. This segmentation allows voltage stress to be confined to only the active memory segment being programmed or erased, protecting other segments and supporting circuitry from high voltage stress, thereby preventing breakdown in smaller geometry devices.
Solution Approach 2:
The patent employs carefully controlled voltage parameters with specific magnitude and polarity combinations during programming and erasing operations. This parameter control minimizes the voltage stress experienced by smaller geometry transistors, preventing voltage breakdown while maintaining the ability to perform programming and erasing operations.
Data Source
AI summary
A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation..