N-Channel Shift Register for Memory Data Shifting
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Solution Overview
Problem
Previous approaches to shifting data in semiconductor memory devices require complementary p-channel transistors, leading to increased die size and power consumption, making them incompatible with on-pitch integration with sense lines and other components.
Innovation Solution
The implementation of a shift register mechanism that shifts data without complementary p-channel transistors, using pre-charge lines and signal control lines to enable n-channel transistors, allowing for data movement within the memory device without external processing resources, thereby reducing power consumption and increasing parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If complementary p-channel transistors are used for data shifting, then data shifting function is achieved, but die size increases
Solution Approach 1:
The patent extracts and eliminates the complementary p-channel transistors from the data shifting circuit, retaining only the essential n-channel transistors. This removal of unnecessary components directly reduces the die size while preserving the core data shifting functionality through alternative circuit design.
Solution Approach 2:
The patent changes the circuit configuration parameters by using single-polarity transistors instead of complementary transistors. This parameter change in the transistor architecture enables data shifting with reduced component count and smaller area occupation.
2Ease of manufacture
If complementary p-channel transistors are used for data shifting, then data shifting function is achieved, but power consumption increases
Solution Approach 1:
By removing the complementary p-channel transistors from the circuit, the patent eliminates the power consumption associated with these additional active components. The simplified single-polarity transistor design reduces overall power usage while maintaining data shifting capability.
3Productivity
If data shifting is performed outside memory array, then data movement is achieved, but processing time increases
Solution Approach 1:
The patent merges the data shifting function with the memory array structure by integrating shift registers directly into the memory cells. This consolidation eliminates separate data movement pathways and external processing steps, enabling simultaneous storage and shifting operations that reduce processing time.
Solution Approach 2:
The memory array is designed to perform multiple functions including data storage, data shifting, and data processing within the same structure. This multi-functionality eliminates the need for separate external processing resources and reduces the time required for data movement and manipulation.
4Productivity
If external processing resources are used, then data processing is achieved, but device complexity increases
Solution Approach 1:
The patent combines processing resources with the memory array structure, creating an integrated system where storage and processing coexist. This merging eliminates separate external processing units and their associated interconnects, reducing overall device complexity while maintaining processing capability.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.