N-Dimensional Grid Network Routing for Chip-to-Chip Communication
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Solution Overview
Problem
Inter-chip communication delays in computer systems are becoming a significant bottleneck due to the mismatch between increasing microprocessor clock speeds and chip-to-chip communication speeds, leading to prolonged memory access latency and processor stalls, despite efforts like large on-chip caches and out-of-order execution.
Innovation Solution
An n-dimensional grid network system with multiple independent communication networks that route data in only two orthogonal directions, preventing deadlocks by ensuring no cycles can be formed, and using a routing mechanism that dynamically adjusts data paths based on headers indicating horizontal and vertical steps to destinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-dimensional grid network is used for chip-to-chip communication, then communication throughput and latency are improved, but routing mechanism complexity increases due to collision handling, load-balancing, and deadlock avoidance requirements
Solution Approach 1:
The communication network is segmented into multiple independent directional networks (e.g., North-East, North-West, South-East, South-West), where each network handles data flow in specific directions only. This segmentation eliminates bidirectional communication conflicts and simplifies routing by assigning dedicated paths for different directions, thereby reducing routing mechanism complexity while maintaining high communication speed.
Solution Approach 2:
The routing mechanism employs asymmetric directional constraints where each communication network is designed to operate in only two opposite directions (e.g., North and East for one network, South and West for another). This asymmetric design prevents cyclic dependencies and deadlock conditions, simplifying the routing logic while achieving fast chip-to-chip communication through optimized directional paths.
2Productivity
If large on-chip caches and out-of-order execution are implemented, then processor productivity is improved, but memory access latency remains a bottleneck that cannot keep the processor busy
Solution Approach 1:
The patent introduces an additional communication dimension by implementing an n-dimensional grid network (where n > 2) that extends beyond traditional two-dimensional layouts. This higher-dimensional architecture provides more routing paths and communication routes, enabling faster data retrieval from memory systems and reducing the time processors wait for data, thereby maintaining high processor productivity despite increased memory access latency in traditional architectures.
3Productivity
If dynamic routing is used to optimize data paths, then communication efficiency is improved, but the risk of deadlock conditions increases without proper constraints
Solution Approach 1:
The routing mechanism employs asymmetric directional constraints where each communication network is designed to operate in only two opposite directions (e.g., North and East for one network, South and West for another). This asymmetric design prevents cyclic dependencies and deadlock conditions, simplifying the routing logic while achieving fast chip-to-chip communication through optimized directional paths.
Solution Approach 2:
The communication network is segmented into multiple independent directional networks (e.g., North-East, North-West, South-East, South-West), where each network handles data flow in specific directions only. This segmentation eliminates bidirectional communication conflicts and simplifies routing by assigning dedicated paths for different directions, thereby reducing routing mechanism complexity while maintaining high communication speed.
Data Source
AI summary
One embodiment of the present invention provides a system for routing data between integrated circuit devices. This system couples together an n-dimensional grid of integrated circuit devices using multiple independent communication networks, wherein each of the communication networks only moves data in two orthogonal directions (e.g., North and East, North and West, South and East, or South and West). The system also includes a routing mechanism that routes data across these communication networks, as well as, into, out of, and through integrated circuits within the n-dimensional grid of integrated circuits. Note that the process of routing a signal across a given network is greatly simplified because it is not possible to create a cycle that causes a deadlock within a given network.