N-Dipole Gate Dielectric Tuning for Stacked Transistor Thresholds
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Solution Overview
Problem
The challenge in the integrated circuit (IC) industry is to provide ICs with multiple threshold voltages for enhanced performance and reduced power consumption, particularly for multigate devices like fin-like field effect transistors and gate-all-around transistors, where minimal space limits the tuning of threshold voltages using different work function metals, and existing dipole engineering techniques face challenges in further scaling and maintaining electrical performance.
Innovation Solution
The introduction of n-dipole dopants such as strontium, erbium, and magnesium, which can be driven into the gate dielectric at low temperatures, allowing for low-temperature threshold voltage tuning of transistors without degrading the electrical performance of already fabricated devices, and enabling multiple threshold voltage tuning for both n-type and p-type transistors with a single work function metal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different work function metals are used to tune threshold voltages of multigate devices, then multiple threshold voltages can be achieved, but device complexity increases and manufacturing becomes more difficult due to minimal space available
Solution Approach 1:
The patent changes the physical-chemical parameters of the gate dielectric by introducing dipole layers with specific dipole moments. This allows threshold voltage tuning through material property modification rather than using different metals, thereby achieving multiple threshold voltages without increasing device structural complexity
Solution Approach 2:
The dipole layer acts as an intermediary between the gate electrode and channel, mediating the electric field to achieve threshold voltage tuning. This intermediary approach eliminates the need for different work function metals while maintaining the ability to tune threshold voltages
2Productivity
If device stacking is implemented to realize further scaling, then integration density increases, but dipole engineering techniques become more challenging to implement
Solution Approach 1:
The patent applies dipole engineering to individual transistors within the stacked structure independently. Each transistor in the stack can be tuned separately using the dipole layer approach, making the technique compatible with device stacking and high integration density
Solution Approach 2:
The dipole layer approach provides a universal threshold voltage tuning mechanism that works across different transistor types and stacking configurations, eliminating the need for type-specific tuning methods and simplifying manufacturing for scaled architectures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible and efficient threshold voltage tuning of transistors at lower temperatures, minimizing the impact on existing devices and improving performance by eliminating the need for high-temperature processing, thus suitable for advanced IC technology nodes like 3 nm and below.
Implementation Method 1
n-dipole dopants such as strontium, erbium, and magnesium, which can be driven into the gate dielectric at low temperatures
Data Source
AI summary
Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high-k/interfacial interface ±0.5 nm.