N-Domino Register with Accelerated Non-Discharge Path Timing
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Solution Overview
Problem
Traditional register circuits in pipeline systems introduce delays due to data-to-output time requirements, constraining the speed of complex logic circuits and limiting the overall speed of the pipeline system, especially in high leakage or high noise environments.
Innovation Solution
The development of non-inverting N-domino registers with accelerated non-discharge paths, which include a domino stage, a write stage, an inverter, a high keeper path, and a low keeper path, utilizing a pulsed clock signal to optimize clock-to-output time and minimize hold time requirements, allowing for faster data transfer without compromising stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional register circuits are used to hold outputs in pipeline stages, then data stability is ensured, but data-to-output time delays increase significantly
Solution Approach 1:
The register circuit is segmented into two independent domino stages: an evaluation stage that computes the logic function and a storage stage that holds the output. This segmentation allows the evaluation stage to operate independently without waiting for the storage stage, reducing the overall data-to-output time while maintaining data stability through the dedicated storage stage.
Solution Approach 2:
The storage stage is pre-charged during the low phase of the clock signal before the evaluation stage produces its output. This preliminary action ensures that the storage stage is ready to immediately capture and hold the evaluation output, eliminating the need for the storage stage to wait for the evaluation to complete, thus reducing the data-to-output time delay.
2Reliability
If register circuits with setup and hold time requirements are used, then stable registered outputs are achieved, but the evaluation circuits are constrained and operating speed decreases
Solution Approach 1:
The circuit uses dynamic logic with clocked pre-charging and evaluation phases. The storage stage is pre-charged dynamically during the low clock phase, and the evaluation stage evaluates during the high clock phase. This dynamic operation eliminates static setup and hold time constraints, allowing evaluation circuits to operate at higher speeds while still achieving stable registered outputs through the clocked capture mechanism.
3Speed
If non-inverting domino registers are used to reduce clock-to-output time, then speed is improved, but hold time requirements are not optimized in high leakage or high noise environments
Solution Approach 1:
The storage stage includes pre-charging circuitry that prepares the storage node during the low clock phase before the evaluation stage produces its output. This pre-charging creates a voltage cushion that protects against leakage currents and noise during the evaluation phase, ensuring stable output in high leakage or high noise environments while maintaining fast clock-to-output time.
Solution Approach 2:
The evaluation logic is extracted from the storage function, with the evaluation stage independently computing the logic function and the storage stage independently holding the output. This extraction allows the storage stage to be optimized for stability with strong pre-charging and holding circuitry, while the evaluation stage can be optimized for speed, achieving both fast clock-to-output time and reliability in challenging environments.
Data Source
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AI summary
An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-charges a pre-charged node high when the symmetric clock signal is low and opens an evaluation window when the pulsed clock signal goes high, and pulls the pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The output stage provides an output signal based on states of the pre-charged node and a second preliminary output node.