N-Path Fractional Frequency Synthesizer for Quantization Noise Suppression

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Solution Overview

Problem

Conventional fractional frequency synthesizers face challenges with quantization errors and noise amplification near the loop bandwidth, which degrade the performance of the frequency synthesizer, especially when trying to suppress high-frequency quantization noise without compromising phase margin.

Innovation Solution

A frequency synthesizer design incorporating a N-path filter with multiple paths, each comprising a switch and a path filter, which generates filtered voltages and reduces noise by adding correlated paths, thereby avoiding noise folding and improving phase margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If an additional filter is introduced in the loop to suppress high-frequency quantization noise, then quantization noise suppression is improved, but the phase margin of the overall loop is affected and noise near the bandwidth is amplified

Engineering Contradiction:
Improvequantization noiseVSAvoidphase margin
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The filter function is segmented into N parallel paths, each with its own switch and path filter. This segmentation allows the system to achieve higher-order noise suppression while maintaining phase margin by distributing the filtering function across multiple independent paths that can be controlled separately.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The N-path filter dynamically switches between N different filtering paths using time-division multiplexing. Each path is activated at different time intervals, allowing the system to adaptively suppress quantization noise across different frequency ranges while maintaining stability through controlled switching.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the roll-off degree introduced by the additional filter is limited to first order to reduce negative influence, then phase margin is preserved, but the ability to suppress quantization noise is insufficient

Engineering Contradiction:
Improvephase marginVSAvoidquantization noise suppression
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Multiple first-order filters in N parallel paths are merged to achieve equivalent higher-order noise suppression. By combining the filtering effects of N first-order path filters through time-division multiplexing, the system achieves the noise suppression capability of an Nth-order filter while maintaining the stability benefits of first-order filtering in each individual path.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If conventional fractional frequency synthesizers use SDM output to modulate loop dividing ratio, then frequency synthesis is achieved, but quantization errors are introduced that appear as phase noise

Engineering Contradiction:
Improvefrequency synthesis capabilityVSAvoidphase noise
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The N-path filter acts as an intermediary between the charge pump and voltage control oscillator, filtering the control voltage to remove quantization noise before it reaches the VCO. This intermediary filtering stage prevents the SDM quantization errors from being converted into phase noise by the VCO, while still allowing the fractional frequency synthesis function to operate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10666271B1Frequency synthesizer and method of operating the same
Publication Date: 2020.05.26 BEKEN CORP
  • US10666271B1 patent drawing
  • US10666271B1 patent drawing
  • US10666271B1 patent drawing

AI summary

A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.