N-Phase Clock Timing Circuit for Adjustable PET Scanner Resolution
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Solution Overview
Problem
Existing PET scanners face limitations in adapting timing circuit resolution to generate desired resolutions, particularly due to fixed frequency clocks and the challenge of rejecting noise-induced short pulses, which affects the accuracy of coincidence event detection for image reconstruction.
Innovation Solution
The implementation of an n-phase clock system with a field programmable gate array (FPGA) that allows for selectable frequencies, an n-phase counter, status detection circuit, and output circuit to provide flexible time-stamping and pulse rejection, eliminating the need for analog delay lines and enabling adjustable timing resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed frequency clock is used in the timing circuit, then the circuit structure is simple, but the timing resolution cannot be adjusted to generate desired resolutions
Solution Approach 1:
The patent implements a dynamic clock system where the clock frequency can be adjusted based on desired timing resolution. The system transitions from a fixed frequency clock to a variable frequency clock that can be programmed to operate at different frequencies, allowing the timing circuit to adapt to different resolution requirements while managing complexity through controlled design.
Solution Approach 2:
The patent changes the clock frequency parameter to achieve different timing resolutions. By allowing the clock frequency to be varied rather than fixed, the system can generate desired resolutions by adjusting this key parameter, directly addressing the adaptability requirement while the complexity is managed through the programmable nature of the system.
2Reliability
If analog delay lines are used for pulse rejection, then the circuit can reject short noise pulses, but the device complexity increases and adaptability decreases
Solution Approach 1:
The patent replaces the analog delay line mechanism with a digital processing approach. Instead of using analog timing delays to reject short pulses, the system uses digital counters and logic circuits that can programmatically identify and reject noise pulses based on duration thresholds, thereby eliminating the need for fixed analog delay lines and enabling adaptability.
Solution Approach 2:
The patent introduces dynamic, programmable pulse rejection logic that can adjust its parameters based on the desired timing resolution. The noise rejection capability becomes adaptable rather than fixed, allowing the system to dynamically adjust its noise filtering behavior to match different operational requirements.
3Adaptability or versatility
If the timing circuit uses fixed resolution counters, then the manufacturing is simpler, but the system cannot be easily adapted to generate desired resolutions
Solution Approach 1:
The patent implements a universal timing circuit design that can perform multiple timing resolution functions through programming rather than requiring different hardware configurations. The counter system is designed to be reconfigurable, allowing a single manufactured circuit to adapt to various resolution requirements, thus maintaining ease of manufacture while achieving flexibility.
Solution Approach 2:
The patent makes the counter resolution dynamic and programmable rather than fixed at manufacturing. The system can be configured through software or control signals to operate at different resolutions, transforming a static manufacturing process into a dynamic operational system that adapts to different requirements without requiring different physical circuits.
Data Source
AI summary
A timing circuit for implementation in a medical imaging system such as a PET scanner, and a method of ascribing times to events in such systems, is disclosed. In one embodiment, the timing circuit includes an n-phase clock having n frequencies of operation, wherein the clock is selectable to provide n-signals that each vary at n frequencies, an n-phase counter including n counter elements coupled to the clock, an n-phase status detection circuit including n status circuits coupled to the n-phase clock, and an n-phase output circuit including n-registers coupled to the n-phase clock and respectively coupled to the n-phase counter and to n-phase status detection circuit, wherein n-registers respectively receive the n-clock signals, the n-count signals, and the n-status signals, respectively, and in response respectively provide n-output signals that collectively form an output signal indicative of a time at which the event detection signal experienced the first status change.