N-Polar III-N Transistor Structure for Low On-Resistance Breakdown Control
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Solution Overview
Problem
The design and fabrication of high-performance III-N transistors with high figures of merit are challenging due to issues with electric field uniformity and high on-resistance, limiting their commercialization and efficiency.
Innovation Solution
The implementation of N-polar III-N devices with a III-N depleting layer, which induces a two-dimensional electron gas channel, allows for stable threshold-voltage, low leakage current, and high breakdown voltages while maintaining a small gate-to-drain separation, reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field plate is used to control the electric field in the drain-side access region, then the electric field profile can be managed, but high electric field peaking occurs at corners creating poor electric field uniformity and requiring large gate-to-drain spacing
Solution Approach 1:
The patent introduces a p-type depleting layer with specific doping concentrations (1×10^16 to 1×10^19 atoms/cm³) and thickness (10 nm to 1 µm) to modify the electric field distribution. This parameter change in the semiconductor structure replaces the field plate approach, achieving uniform electric field control without requiring large gate-to-drain spacing, thus resolving the contradiction between reliability and device dimensions.
2Ease of manufacture
If typical III-N device structures are used, then fabrication is straightforward, but high on-resistance limits efficiency and power handling capability
Solution Approach 1:
The patent creates a composite structure by integrating a p-type depleting layer with the standard III-N heterostructure (n-type channel layer and barrier layer). This composite material approach forms a pn junction that enables conductivity modulation, significantly reducing on-resistance while maintaining ease of manufacture through conventional III-N fabrication processes.
3Loss of energy
If the gate-to-drain spacing is reduced to lower on-resistance, then power handling efficiency improves, but electric field uniformity deteriorates leading to breakdown
Solution Approach 1:
The p-type depleting layer acts as an intermediary between the gate and drain regions, forming a pn junction that modulates conductivity in the drain-side access region. This intermediary structure enables reduced gate-to-drain spacing while maintaining breakdown voltage through controlled conductivity modulation, resolving the contradiction between low on-resistance and high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables III-N transistors with improved conductivity, reduced on-resistance, and increased breakdown voltage, facilitating faster switching times and more efficient power handling.
Implementation Method 1
The III-N material structure of device 200 includes a III-N buffer layer 11 formed over a suitable substrate 10. The III-N channel layer 15 is formed over the III-N buffer layer and the III-N barrier layer 14 is formed over the III-N channel layer 15. The bandgap of the III-N barrier layer 14 is greater than the bandgap of the III-N channel layer 15.
Data Source
AI summary
Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.