N-Port Memory Circuit Parallel-to-Serial Conversion

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Solution Overview

Problem

Typical multi-port SRAM circuits occupy a relatively large area compared to single-port SRAM circuits, limiting their practical application due to the need for increased space for higher-order port capabilities.

Innovation Solution

The implementation of N-port memory circuits using up-sampling and down-sampling logic to allow M memory addresses to be accessed concurrently, where M is greater than N, by converting parallel inputs into serial sets and processing them sequentially, enabling higher data access rates with a smaller chip area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-port SRAM circuits are used to allow concurrent access to multiple memory locations, then the data access rate is improved, but the chip area occupied increases significantly

Engineering Contradiction:

Improvedata access rateVSAvoidchip area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent applies dynamic frequency transformation by converting parallel inputs at frequency F1 into serial sets at frequency F2 (where F2 = M/N × F1), allowing a single-port memory to dynamically process M concurrent accesses through temporal multiplexing rather than requiring M physical ports simultaneously

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent transforms the problem from spatial dimension (M parallel ports side-by-side) to temporal dimension (M serial accesses over time), using up-sampling logic to convert M parallel address inputs into N sets of M/N serial addresses that are processed sequentially by a single-port memory

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If higher-order multi-port memories are used to support larger numbers of simultaneous accesses, then the productivity is improved, but the device complexity increases

Engineering Contradiction:

Improvesimultaneous accessesVSAvoidcircuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent makes a single-port memory perform multiple functions by enabling it to process M concurrent accesses through frequency transformation and serializing logic, replacing the need for dedicated M-port memory circuits with a universal single-port memory controller that handles multiple access patterns

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the memory system by transforming the frequency domain (from F1 to F2 = M/N × F1) and the data format (from parallel to serial), allowing the same physical memory resource to achieve higher throughput without increasing port count

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7529139B2N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof

Publication Date: 2009.05.05 MEDIATEK INC

AI summary

Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a higher-order multi-port memory can be replaced by a lower-order multi-port or single-port memory. Consequently, smaller chip area or higher data access rate can be achieved.