N-type CNT Transistor Fabrication via MgO Acidization
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Solution Overview
Problem
Current methods for producing N-type thin film transistors using carbon nanotubes face challenges such as instability and dopant diffusion, leading to performance degradation and reduced integrated circuit performance.
Innovation Solution
A method involving the deposition of a magnesia (MgO) layer, followed by acidization to form a first dielectric layer, and subsequent application of a semiconductor carbon nanotube layer, source and drain electrodes, a second dielectric layer, and a gate electrode, which isolates the carbon nanotubes from air and introduces N-type properties through controlled doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical doping methods are used to create N-type carbon nanotube transistors, then N-type characteristics can be achieved, but long-term stability is compromised and dopant diffusion pollution occurs
Solution Approach 1:
The patent extracts and removes the harmful dopant elements from the system by using plasma treatment to eliminate P-type doping characteristics from carbon nanotubes, thereby achieving N-type characteristics without introducing dopant diffusion pollution
Solution Approach 2:
The patent introduces plasma as an intermediary medium to transfer nitrogen-containing groups to carbon nanotubes, enabling N-type doping without direct contact with dopant materials that would cause diffusion pollution
2Reliability
If low-work function metal deposition is used as electrode to achieve N-type characteristics, then N-type properties can be obtained, but the N-type unipolar characteristic becomes不明显 (not obvious)
Solution Approach 1:
The patent changes the chemical composition parameters of carbon nanotubes by introducing nitrogen-containing functional groups through plasma treatment, fundamentally altering their electronic properties to achieve clear N-type unipolar characteristics
3Reliability
If carbon nanotubes are used as intrinsic semiconductor, then excellent electrical and mechanical properties are achieved, but under normal air conditions they behave as P-type semiconductor
Solution Approach 1:
The patent creates an inert nitrogen-rich environment on the carbon nanotube surface through plasma treatment with nitrogen-containing gases, protecting the intrinsic semiconductor properties from degradation by ambient air and preventing unwanted P-type behavior
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability and N-type characteristics of the thin film transistor, reducing performance losses and enabling the transition from P-type to N-type carbon nanotube devices, facilitating improved integration and performance in integrated circuits.
Implementation Method 1
depositing a magnesia (MgO) layer on a surface of the insulating substrate
Implementation Method 2
forming a first dielectric layer by acidizing the MgO layer
Implementation Method 3
locating a semiconductor carbon nanotube layer to cover the dielectric layer
Implementation Method 4
applying a source electrode and a drain electrode to be electrically connected to the semiconductor carbon nanotube layer
Implementation Method 5
forming a second dielectric layer on the semiconductor carbon nanotube layer
Implementation Method 6
applying a gate electrode on the second dielectric layer
Data Source
AI summary
A method of making N-type semiconductor layer includes following steps. An insulating substrate is provided. An MgO layer is deposited on the insulating substrate. A first dielectric layer is formed by acidizing the MgO layer. A semiconductor carbon nanotube layer is formed to cover the MgO layer. A source electrode and drain electrode are formed to be electrically connected to the semiconductor carbon nanotube layer. A second dielectric layer is applied on the semiconductor carbon nanotube layer. A gate electrode is formed on the second dielectric layer.


