N-type HEMT Driver Circuit Under-Voltage Lockout Protection
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Solution Overview
Problem
High voltage applications using silicon-based gate drivers for wide-bandgap semiconductor switching devices face challenges in protecting against under-voltage conditions, which can lead to uncontrolled switching and potential damage, and existing solutions are inefficient in manufacturing and prone to parasitic inductance issues.
Innovation Solution
A driver circuit based on n-type high electron mobility transistors (HEMTs) is designed to detect under-voltage conditions and implement an under-voltage lockout mode, using a voltage divider and detection circuit to generate signals that disable high voltage device switching, thereby providing protection without requiring additional masks for p-type devices and reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If silicon-based gate drivers are used to drive wide-bandgap semiconductor switching devices, then the switching devices can operate at high voltages, but the system becomes vulnerable to uncontrolled switching under under-voltage conditions
Solution Approach 1:
The driver circuit performs preliminary detection of the power supply voltage level through the voltage divider network before allowing switching operations. The UVLO detection circuit proactively identifies under-voltage conditions and prevents uncontrolled switching by disabling the gate driver output, rather than reacting after damage occurs.
Solution Approach 2:
A voltage divider network acts as an intermediary between the high voltage power supply and the detection circuit. This intermediary scales down the high voltage to a safe level for detection while providing electrical isolation, enabling reliable UVLO protection without exposing sensitive components to dangerous voltage levels.
2Reliability
If additional masks for p-type devices are used in manufacturing, then UVLO protection can be implemented, but manufacturing efficiency decreases and parasitic inductance increases
Solution Approach 1:
The driver circuit uses only n-type HEMTs for all switching devices, creating a homogeneous device type throughout the circuit. This eliminates the need for additional photomasks required for fabricating p-type devices, streamlining the manufacturing process while maintaining UVLO protection functionality through the integrated detection circuit.
Solution Approach 2:
The UVLO detection circuit is merged with the main driver circuit functionality, sharing common n-type HEMTs and circuit structures. This integration combines multiple functions (switching and UVLO detection) into a single unified circuit, eliminating separate protection circuits and reducing overall device complexity.
3Ease of manufacture
If n-type HEMTs are used instead of p-type devices, then manufacturing efficiency improves and parasitic inductance is reduced, but the circuit design becomes more complex
Solution Approach 1:
The n-type HEMTs in the driver circuit serve multiple functions: they act as both the main switching devices and the UVLO detection switches. The same transistor structures and fabrication processes are used throughout, making the circuit universal in its approach and eliminating the need for separate p-type device fabrication streams.
Data Source
AI summary
A circuit includes a protection circuit and a gate driver coupled to a power supply voltage node configured to have a power supply voltage level. The protection circuit generates a first signal having a first logical voltage level when the power supply voltage level is equal to or greater than a threshold voltage level, and having a second logical voltage level when the power supply voltage level is less than the threshold voltage level. The gate driver receives the first signal and a second signal, and, when the first signal has the first logical voltage level, outputs a third signal based on the second signal, and when the first signal has the second logical voltage level, outputs the third signal having a predetermined one of the first or second logical voltage levels.