N-type TFT Gate Thickness Variation for Leakage Reduction
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Solution Overview
Problem
Conventional methods for manufacturing low-temperature polysilicon N-type thin film transistors have complex processes, high fabrication costs, and result in significant leakage currents, affecting the sensitivity and display performance of OLED panels.
Innovation Solution
The proposed solution involves an N-type thin film transistor structure with a poly-silicon layer, a gate layer, source, and drain, where the gate layer partially overlaps the source and drain regions, and the source and drain regions include both heavily- and lightly-doping regions. The manufacturing method involves ion implantation using the gate layer as a mask to form doping regions, with a thinner gate layer on the lightly-doping regions to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate layer thickness is uniform across source/drain and channel regions, then the manufacturing process is simple, but large leakage current occurs in off state reducing transistor sensitivity
Solution Approach 1:
The gate layer is designed with different thicknesses in different regions: a first thickness in the channel region and a second thickness (smaller than the first) in the source/drain regions. This local variation in gate layer properties reduces leakage current in the off state while maintaining proper channel control, thereby improving transistor sensitivity without requiring complete process redesign
Solution Approach 2:
The gate layer thickness is made dynamic rather than uniform, allowing the electric field distribution to be optimized locally. The thinner gate over source/drain regions creates a dynamic electric field profile that reduces carrier attraction in off state, while the thicker gate over the channel maintains proper switching control
2Manufacturing precision
If two masks are used to define N+ region and N- region separately, then precise doping regions are achieved, but the manufacturing process becomes complicated and costly
Solution Approach 1:
The patent combines the definition of N+ region and N- region into a single masking step. The gate layer structure itself (with its thickness variations) serves as the masking element, eliminating the need for separate masks for N+ and N- regions. This merging of functions maintains precise doping region definition while significantly simplifying the manufacturing process
Solution Approach 2:
The gate layer is given multiple functions: it serves as both the functional gate electrode and as the masking layer for ion implantation. The thickness variations in the gate layer provide the necessary patterning information for creating both N+ and N- regions simultaneously, reducing the number of dedicated masking steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current by minimizing the electric field intensity and electron attraction, thereby improving the transistor's properties and simplifying the manufacturing process, while also reducing fabrication costs.
Implementation Method 1
The manufacturing method involves ion implantation using the gate layer as a mask to form doping regions
Data Source
AI summary
The disclosure provides an N-type thin film transistor, including a poly-silicon layer, a gate layer, a source and a drain. The poly-silicon layer includes a channel region, a source region and a drain region at two side of the channel region. The gate layer is on the channel region, a projection of the gate layer on the poly-silicon layer partially overlaps the source region and the drain region, and a thickness of the gate layer on the source region and the drain region are smaller than a thickness of the gate layer on the channel region. The source region and the drain region both include a heavily-doping region and a lightly-doping region connected to the heavily-doping region, the source and the drain are respectively on the heavily-doping region of the source region and the drain, and respectively electrically connects to the heavily-doping region of the source region and the drain.