Non-Uniform N-Well Width for SRAM Well Pick-Up Resistance
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Solution Overview
Problem
As semiconductor technology advances, the scaling down of ICs leads to increased leakage between adjacent n-type and p-type wells due to dopant diffusion, resulting in higher well pick-up resistance and deteriorated latch-up performance in SRAM macros, which existing well pick-up region designs fail to adequately address.
Innovation Solution
The placement of n-wells and p-wells in memory macro well pick-up regions is optimized by expanding the width of n-wells in n-type WPU regions and reducing the number of contact features, thereby reducing well pick-up resistance without compromising p-well performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit geometry is scaled down to increase functional density, then production efficiency is improved and costs are reduced, but leakage between adjacent n-wells and p-wells increases due to dopant diffusion
Solution Approach 1:
The patent applies local quality by making the n-well width non-uniform: wider in the well pick-up region and narrower in the memory bit cell region. This localized dimensional variation allows the n-well to provide better挑出 (pick-up) performance in the WPU region while maintaining proper functionality in the memory cell region, thereby addressing the leakage issue locally without affecting overall device performance.
Solution Approach 2:
The patent changes the geometric parameter of the n-well width along its length. Specifically, the n-well has a first width in the memory bit cell region and a second, larger width in the well pick-up region. This parameter change increases the n-well's ability to pick up carriers and reduce leakage in the WPU region while maintaining compatibility with scaled-down geometry elsewhere.
2Stability of the object's composition
If well pick-up regions are designed to stabilize well potential, then uniform charge distribution is achieved, but n-well and p-well resistance increases due to dopant diffusion in advanced process nodes
Solution Approach 1:
The patent makes the n-well structure non-uniform by providing a wider section in the well pick-up region and a narrower section in the memory bit cell region. This local quality variation allows the n-well to maintain stability in the WPU region while reducing resistance and improving latch-up performance, resolving the contradiction between stability and reliability.
Solution Approach 2:
The patent addresses the resistance issue by extending the n-well in the vertical dimension (width) specifically in the well pick-up region. This dimensional change increases the cross-sectional area for carrier transport in the WPU region, thereby reducing resistance and improving latch-up performance without affecting the memory cell operation.
3Area of stationary object
If contact features are reduced to save chip area, then manufacturing cost is reduced, but well pick-up resistance may increase
Solution Approach 1:
The patent compensates for reduced contact features by changing the n-well width parameter in the well pick-up region. The increased width provides a larger effective area for carrier collection, which compensates for having fewer contact features and maintains low well pick-up resistance while saving chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates the negative impact of diffusion areas on well pick-up resistance, reducing n-well pick-up resistance by one to two orders while maintaining p-well pick-up resistance, and saves chip area by reducing the number of contact features.
Implementation Method 1
leakage between adjacent n-type wells (or n-wells) and p-type wells (or p-wells) becomes more severe due to dopant diffusion
Data Source
AI summary
Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.