N2HET-HTU ADC Capture Around SPI and EMIF Speed Limits
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Solution Overview
Problem
Traditional analog to digital conversion systems using external ADCs face limitations due to slow serial peripheral interface (SPI) and external memory interface (EMIF), which can lead to bottlenecks in high-speed data transfer, especially in demanding applications like motor control, causing system unreliability and CPU intervention.
Innovation Solution
The method employs a high-end timer unit (N2HET) and High-End Timer Transfer Unit (HTU) to perform ADC data conversion and acquisition without CPU intervention, by connecting conversion start, chip select, read enable, and data pins of the ADC with N2HET pins, and using HTU requests to transfer data from N2HET RAM to CPU RAM, thereby overcoming SPI and EMIF limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SPI bus is used for ADC data transfer, then device compatibility is improved, but data transfer speed deteriorates
Solution Approach 1:
The patent introduces N2HET as an intermediary device between the ADC and CPU. The N2HET receives conversion requests, controls the ADC conversion process, and manages data transfer through HTU, eliminating the need for CPU intervention and enabling high-speed parallel data transfer while maintaining compatibility with external ADC devices.
Solution Approach 2:
The patent replaces the software-based SPI control mechanism with a hardware-based N2HET control system. The N2HET uses dedicated hardware circuits to generate control signals for ADC conversion and employs HTU for direct memory access, substituting the slow serial software polling method with fast parallel hardware-controlled transfer.
2Speed
If EMIF is used for ADC data transfer, then data transfer speed is improved, but system complexity increases
Solution Approach 1:
The patent combines the timer function (N2HET) and data transfer function (HTU) into a single integrated system. The N2HET generates conversion requests and the HTU automatically transfers data to predetermined memory locations, merging control and data transfer operations into one coordinated hardware system that simplifies the overall architecture compared to separate EMIF and DMA configurations.
Solution Approach 2:
The N2HET system operates autonomously without CPU intervention. It self-generates conversion requests based on timer events, controls the ADC conversion process, and automatically triggers HTU to transfer data to memory. This self-service capability reduces system complexity by eliminating the need for CPU software management of the data transfer process.
3Ease of operation
If CPU is used for ADC data acquisition, then control flexibility is improved, but system reliability deteriorates
Solution Approach 1:
The patent extracts the ADC data acquisition function from the CPU and assigns it to the dedicated N2HET module. The N2HET handles conversion requests, ADC control, and data transfer operations independently, freeing the CPU from these time-consuming tasks and improving system reliability by reducing CPU interruptions and potential software errors.
Solution Approach 2:
The patent assigns specific functions to specialized hardware modules: N2HET for timing and control, HTU for data transfer, and CPU for high-level processing. This division of labor gives each component optimized local capabilities - the N2HET provides precise timing control while the CPU maintains flexibility for complex decision-making, achieving both reliability and control flexibility.
4Loss of time
If DMA is used for EMIF data transfer, then CPU time is saved, but DMA bandwidth becomes limited
Solution Approach 1:
The patent uses N2HET to preliminarily prepare for data transfer by generating conversion requests in advance based on timer events. The HTU is pre-configured with source and destination addresses, and data transfer is automatically triggered when conversion completes, eliminating the need for CPU software setup and maximizing DMA bandwidth utilization through pre-planned transfer operations.
Data Source
AI summary
A method of converting and acquiring external analog data without central processing unit (CPU) intervention using high-end timer unit (N2HET) and High End Timer Transfer Unit (HTU) to overcome serial peripheral interface (SPI) and external memory interface (EMIF) limitations encountered while performing high speed transfers. The method includes connecting a conversion start pin, a chip select (CS) pin, a read enable pin, a converter busy pin and data pins of an analog to digital converter (ADC) with the pins of the N2HET. The N2HET is configured to perform ADC data conversion and acquisition by performing steps of: activating a conversion start signal on the CS pin until a deactivation of the converter busy pin; and generating an HTU request to transfer data from a data N2HET pin to a N2HET random access memory (RAM) unit via a data transfer channel and then from N2HET RAM to RAM of the CPU.