NAC Frame Transmission Control for Interconnection Protocol Error Handling
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Solution Overview
Problem
Current interconnection interface technologies, such as the MIPI M-PHY and UniPro specifications, face challenges in efficiently handling errors in high-speed data transmission over multiple lanes, particularly in scenarios where multiple frames are received in each clock cycle, leading to incorrect NAC frame transmission and potential violations of the UniPro specification.
Innovation Solution
A method and controller architecture that receive frame error and correction position indication signals to determine the occurrence of frame errors, enabling or disabling NAC frame transmission based on these signals, and comparing them across clock cycles to ensure accurate error handling and compliance with the UniPro specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple frames are received in each clock cycle to increase transmission efficiency, then productivity is improved, but reliability deteriorates due to incorrect NAC frame transmission
Solution Approach 1:
The patent segments the error handling process into distinct stages: error detection through indication signals, NAC frame transmission control, and state management. By dividing the processing of multiple frames into individual error handling units, each frame error can be independently identified and addressed, preventing incorrect NAC transmissions while maintaining efficient multi-frame processing
Solution Approach 2:
The patent implements feedback mechanisms through frame error position indication signals and frame correction position indication signals. These signals provide real-time feedback about error locations and correction status, enabling the system to adjust NAC frame transmission accordingly. The feedback loop ensures that NAC frames are transmitted only when appropriate, maintaining reliability while processing multiple frames per clock cycle
2Reliability
If NAC frame transmission is enabled to notify errors actively, then reliability is improved, but device complexity increases due to additional control signals and states
Solution Approach 1:
The patent extracts the error notification function into a dedicated NAC frame transmission mechanism, separating it from the general data transmission process. By taking out the error handling logic into distinct indication signals and control states, the system achieves reliable error notification without unnecessarily complicating the overall transmission protocol
Solution Approach 2:
The patent employs preliminary actions by generating frame error position indication signals and frame correction position indication signals before NAC frame transmission is needed. These preliminary signals prepare the system by identifying error locations and correction status in advance, allowing NAC frames to be transmitted only when truly necessary, thus reducing unnecessary control signal complexity
Data Source
AI summary
A method for error handling of an interconnection protocol, a controller, and a storage device are provided. The method includes receiving a frame error position indication signal to indicate whether an error occurs in a frame in each clock cycle and a symbol position corresponding to the error, and receiving a frame correction position indication signal to indicate whether the frame in each clock cycle is correct and a symbol position corresponding to the frame that is correct; according to the frame error position indication signal and the frame correction position indication signal, determining that a frame error occurs in a first clock cycle, and after requesting for NAC frame transmission, sending a request for disabling the NAC frame transmission; and after the first clock cycle, comparing the frame error position indication signal and the frame correction position indication signal.