Named Barrier Mechanism for GPU Thread Synchronization

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Solution Overview

Problem

Conventional GPU synchronization barriers can only be defined once per workgroup, leading to inefficiencies as they must wait for all threads to reach a synchronization point, even if only a subset is involved in a producer-consumer relationship, limiting the number of signal messages that can be in flight.

Innovation Solution

Implementing a named barrier mechanism that allows multiple independent synchronization barriers within a thread workgroup, enabling each thread to have multiple signal messages for different named barriers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single barrier is defined per workgroup, then synchronization is ensured for all threads, but threads must wait for all threads to reach the synchronization point even if only a subset is involved in a producer-consumer relationship

Engineering Contradiction:
Improvesynchronization correctnessVSAvoidthread wait time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides a single workgroup barrier into multiple independent named barriers (e.g., barrier_A, barrier_B, barrier_C), each serving specific thread subsets. This segmentation allows threads to synchronize only with relevant peers rather than waiting for all threads, resolving the contradiction between synchronization correctness and thread wait time.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a single barrier is defined per workgroup, then all threads are synchronized, but the number of signal messages that can be in flight is limited

Engineering Contradiction:
Improvesynchronization completenessVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the single barrier into multiple named barriers, the system enables multiple independent signal messages to be in flight simultaneously across different barrier instances. This increases throughput while maintaining synchronization completeness for each named barrier's thread subset.

Inventive Principle:
Principle #1Segmentation

3Reliability

If all threads must reach a single synchronization point, then full workgroup synchronization is achieved, but threads involved in specific producer-consumer relationships cannot proceed independently

Engineering Contradiction:
Improveworkgroup synchronizationVSAvoidthread independence
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent creates multiple named barriers that segment the workgroup into different synchronization domains. Threads can join specific named barriers based on their producer-consumer relationships, achieving workgroup synchronization where needed while maintaining thread independence for specific communication patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different named barriers provide different synchronization semantics tailored to specific thread subsets and their local communication needs. This allows threads to have customized synchronization behavior appropriate to their specific producer-consumer relationships rather than uniform workgroup-wide synchronization.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11409579B2Multiple independent synchonization named barrier within a thread group
Publication Date: 2022.08.09 INTEL CORP
  • US11409579B2 patent drawing
  • US11409579B2 patent drawing
  • US11409579B2 patent drawing

AI summary

An apparatus to facilitate thread barrier synchronization is disclosed. The apparatus includes a plurality of processing resources to execute a plurality of execution threads included in a thread workgroup and barrier synchronization hardware to assign a first named barrier to a first set of the plurality of execution threads in the thread workgroup, assign a second named barrier to a second set of the plurality of execution threads in the thread workgroup, synchronize execution of the first set of execution threads via the first named barrier and synchronize execution of the second set of execution threads via the second named barrier.