Memory Control Circuit with Namespace Mapping for 16 TB Arrays
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Solution Overview
Problem
Existing memory cell arrays with capacities of 16 TB or higher face the challenge of maintaining 32-bit addressing while ensuring write efficiency, as endurance group addressing technologies halve the writing efficiency due to interference between groups.
Innovation Solution
A memory control circuit utilizing a namespace-table, logical-to-virtual-mapping-table, and virtual-to-physical-block-table enables 16 TB memory cell arrays to use 32-bit virtual addresses without increasing addressing bits, through mapping and conversion processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If endurance group addressing technology is used to maintain 32-bit addressing for 16 TB memory, then addressing bit count is maintained, but write efficiency is halved due to interference between groups
Solution Approach 1:
The patent segments the memory addressing space into multiple namespaces, each with its own mapping table. This allows the system to maintain 32-bit addressing within each namespace while supporting larger total capacity through multiple segments. The segmentation eliminates the interference problem by isolating different address spaces into separate manageable units.
Solution Approach 2:
The patent introduces an additional dimension to the addressing structure by adding namespace identification to the traditional address structure. Instead of simply extending the address bus, it creates a multi-dimensional addressing space where data can be accessed through namespace + offset, effectively increasing addressing capacity without increasing bit width in the traditional sense.
2Quantity of substance
If addressing bits are increased to support 16 TB capacity, then memory capacity is supported, but addressing complexity and hardware requirements increase
Solution Approach 1:
The patent divides the large address space into multiple smaller namespaces, each managed by its own mapping table. This segmentation allows the system to support large total capacity (16 TB or more) while keeping each individual address translation operation simple and confined to 32-bit addresses within a namespace.
Solution Approach 2:
The patent introduces mapping tables as intermediary structures between the physical memory and the logical address space. These mapping tables act as mediators that translate simple 32-bit offsets into actual physical addresses, eliminating the need for complex direct addressing of large capacities.
3Device complexity
If endurance group addressing is implemented, then 32-bit addressing is maintained, but channel utilization is reduced to half
Solution Approach 1:
The patent implements dynamic address mapping where the mapping tables can be flexibly configured and updated. This dynamic approach allows the system to adaptively manage channel utilization by redirecting address mappings to optimize data flow, preventing the static channel utilization limitations of endurance group addressing.
Solution Approach 2:
The patent changes the addressing parameter structure by introducing namespace identification as a separate parameter from the address offset. This parameter separation allows independent optimization of addressing width (maintained at 32 bits) and channel utilization (improved through flexible namespace management and mapping).
Data Source
AI summary
A memory device and a memory control circuit are provided. The memory control circuit is used to control a memory cell array. A processing circuit of the memory control circuit is configured to obtain a mapping group identification according to a namespace identification and a logical address through a namespace-table. The processing circuit is configured to obtain a block group identification and a mapping entry through a logical-to-virtual-mapping-table according to the mapping group identification and the offset of the logical address in the mapping group identification. The processing circuit is configured to obtain a super block identification according to the block group identification and the virtual block number through a virtual-to-physical-block-table. The processing circuit is configured to obtain a physical block number according to the super block identification, a channel, a die and a plane through the virtual-to-physical-block-table.