Namespace Error-Checking in Storage Address Translation

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Solution Overview

Problem

Conventional storage systems lack efficient management of logical block addresses, making it difficult to delete and reassign storage regions, as each logical block address is independent, leading to inefficient resource allocation and management.

Innovation Solution

Implementing namespaces in a memory subsystem, where physical addresses are error-checked using a namespace identifier and offset, allowing for efficient creation and deletion of namespaces without disrupting error-checking, and using hierarchical tables to manage logical to physical address translations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional storage systems use independent logical block addresses, then each address can be accessed independently, but storage region deletion and reassignment becomes inefficient

Engineering Contradiction:
Improvestorage allocation efficiencyVSAvoidaddress management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the storage address space into namespaces, where each namespace is a contiguous range of logical block addresses assigned to specific host systems or processes. This segmentation allows efficient management of storage regions by enabling deletion and reassignment at the namespace level rather than at the individual address level, directly resolving the contradiction between storage allocation efficiency and address management complexity

Inventive Principle:
Principle #1Segmentation

2Productivity

If namespaces are introduced to improve storage management, then storage allocation efficiency improves, but error-checking reliability may be compromised

Engineering Contradiction:
Improvestorage allocation efficiencyVSAvoiderror-checking reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges the namespace identifier and offset into a unified logical address structure. The logical address consists of the namespace identifier followed by the offset within that namespace, creating a combined address format that preserves error-checking capabilities while enabling efficient namespace-based storage management. This merging approach allows the system to maintain reliability by ensuring that error-checking mechanisms can still validate addresses within the hierarchical namespace structure

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If hierarchical tables are used for address translation, then name space management capability improves, but system complexity increases

Engineering Contradiction:
Improvenamespace management capabilityVSAvoidaddress translation structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a hierarchical table structure for address translation, organizing the translation process across multiple levels or dimensions. This hierarchical approach enables sophisticated namespace management capabilities by breaking down the complex address translation task into manageable levels, where each level handles specific aspects of the translation, thereby achieving versatility while controlling complexity through structured organization

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11232028B2Error-checking in namespaces on storage devices
Publication Date: 2022.01.25 MICRON TECHNOLOGY INC
  • US11232028B2 patent drawing
  • US11232028B2 patent drawing
  • US11232028B2 patent drawing

AI summary

Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.