NAND Memory Read Operations with Adaptive Reference Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-density NAND flash memory devices, threshold voltage (Vt) distribution shifts due to factors like programmed cell charge loss and noise, leading to read failures as pre-defined read levels fail to track the shifted distribution.
Innovation Solution
A system and method for performing a read operation in NAND memory that adjusts the read voltage based on real-time threshold voltage distribution shifts, using adaptive read reference voltages to accurately determine the state of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pre-defined read levels are used for memory cells, then the read operation is simple and fast, but read accuracy deteriorates due to threshold voltage distribution shifts
Solution Approach 1:
The patent implements dynamic read reference voltage adjustment by performing multiple read operations with different read reference voltages (e.g., first read reference voltage and second read reference voltage) and selecting the correct data based on the result. This dynamic approach allows the system to adapt to threshold voltage distribution shifts while maintaining read speed through parallel processing of multiple voltage levels.
Solution Approach 2:
The patent changes the read reference voltage parameter to track threshold voltage distribution shifts. By using multiple read reference voltages and determining which voltage level corresponds to the current threshold distribution, the system maintains accurate reads despite parameter drift in the memory cells over time.
2Measurement precision
If multiple read operations with different read reference voltages are performed, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the read operation into multiple parallel read operations, each using a different read reference voltage. By dividing the read process into independent voltage-level readings (e.g., first read reference voltage reading and second read reference voltage reading), the system achieves high accuracy through parallel processing rather than sequential complex analysis.
Solution Approach 2:
The patent uses feedback from multiple read operations to determine the correct data. The controller receives read results from multiple voltage levels and uses this feedback to identify the correct logic state, effectively using the outcomes of simpler operations to solve the complexity of accurate reading under varying threshold conditions.
3Quantity of substance
If vertically stacked memory cells are used to increase storage density, then storage density is improved, but reliability deteriorates due to aggressive scaling
Solution Approach 1:
The patent adjusts read reference voltages as a parameter change strategy to compensate for reliability issues in vertically stacked memory cells. By dynamically selecting appropriate read reference voltages that match the current threshold voltage distribution, the system maintains reliable reads even as aggressive scaling affects cell characteristics in three-dimensional stacked architectures.
Data Source
AI summary
A memory device includes a memory array having memory cells, a page buffer coupled to the memory array through bit lines and including a latch, and a control logic coupled to the page buffer. The control logic is configured to perform a first read operation on the memory cells, and perform a second read operation on the memory cells by dividing the memory cells into a plurality of groups of memory cells, and performing a second read operation on the plurality of groups of memory cells based on a first set of develop times. Each of the first set of develop times is different. The control logic is also configured to perform a third read operation on the memory cells by performing a third read operation on the plurality of groups of memory cells based on a second set of develop times. Each of the second set of develop times is different. The control logic is further configured to determine a read develop time based on the third read operation.