Dynamic NAND Memory Address Cycle Configuration
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Solution Overview
Problem
The increasing demand for higher memory density in NAND flash memory devices poses challenges in efficiently addressing and operating large numbers of memory units, particularly as the complexity and performance of electronic systems grow, while maintaining cost-effectiveness and minimizing parts count.
Innovation Solution
The implementation of a memory controller that dynamically selects and configures the number of address cycles, ranging from five to six, based on the density of the NAND memory, using a switching element like a fuse to accommodate varying memory densities and support different memory modes, ensuring backwards compatibility and efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of address cycles is fixed at a predetermined value, then the device complexity is reduced and ease of manufacture is improved, but the adaptability to different memory densities is worsened
Solution Approach 1:
The patent implements a dynamic addressing mechanism where the memory device can switch between different address cycle modes (first mode with fewer address cycles, second mode with more address cycles) based on the actual memory density. This allows the system to adapt its addressing behavior dynamically rather than being fixed, resolving the contradiction between adaptability and complexity by providing multiple predefined configurations that can be selected based on requirements.
Solution Approach 2:
The patent changes the parameter of address cycle count from a fixed value to a variable that can be configured based on memory density. By providing different address cycle modes (e.g., 5-address cycle mode vs. 6-address cycle mode) and allowing selection between them, the system can optimize for different memory densities without requiring a completely different addressing mechanism for each density, thus improving adaptability while controlling complexity.
2Quantity of substance
If more address cycles are used to address individual memory units, then the memory density capability is improved, but the productivity and operation speed are worsened
Solution Approach 1:
The patent implements dynamic selection of address cycle modes based on the actual number of memory units being addressed. When addressing a smaller number of memory units, the system uses the first mode with fewer address cycles for faster operation. When larger memory spaces need to be addressed, it switches to the second mode with additional address cycles. This dynamic adaptation resolves the contradiction by optimizing for speed when possible and expanding capacity when necessary.
3Adaptability or versatility
If a switching element like a fuse is used to configure address cycles, then the adaptability to different densities is improved, but the ease of manufacture and parts count are worsened
Solution Approach 1:
The patent uses a fuse or similar switching element that is configured during the manufacturing process or initial setup. This preliminary configuration determines the address cycle mode before the device enters normal operation. By pre-configuring the addressing mode rather than requiring runtime configuration, the system achieves adaptability to different memory densities while minimizing the impact on manufacturing complexity and parts count.
Data Source
AI summary
Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).