3D Memory Cell Stacking for NAND Area Matching and Density
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Solution Overview
Problem
The increasing number of stack layers in 3D NAND memory devices leads to an area mismatch between the substrate of the memory array device and the CMOS device, resulting in idle utilization space and unfavorable development for next-generation 3D NAND memory due to the need for a larger substrate area.
Innovation Solution
A three-dimensional memory device is formed by stacking at least two memory cells, with each cell comprising a memory array device and a CMOS device electrically connected through a set of contacts, allowing for high storage density without the necessity of stacking numerous memory layers, thereby optimizing the area ratio of the substrates and reducing idle space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stack layers in the memory array device is increased to achieve high storage capacity, then the storage density is improved, but the substrate area of the memory array device is increased, causing area mismatch with the CMOS device and resulting in idle utilization space
Solution Approach 1:
The invention divides the memory system into multiple independent memory cells stacked vertically. Each memory cell contains a memory array device with a specific number of memory layers (first to fourth memory layers) and a CMOS device. By segmenting the memory array into multiple cells rather than using one large array, the substrate area of each memory array device is reduced to match the CMOS device area, eliminating idle space while maintaining high storage capacity through vertical stacking of multiple cells.
Solution Approach 2:
The invention transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Multiple memory cells are stacked vertically along the thickness direction, with each cell containing memory arrays and CMOS devices bonded together. This vertical stacking in the third dimension enables high storage density without increasing the substrate area in the horizontal plane, resolving the area mismatch problem.
2Quantity of substance
If the number of memory layers in the memory array device is increased to improve storage density, then the storage capacity is improved, but the footprint of the step structure is increased, leading to larger substrate area requirements
Solution Approach 1:
The memory array is segmented into multiple discrete memory cells, each containing a limited number of memory layers (four layers per cell). Instead of creating one large memory array with many layers that would require a large footprint, the invention divides the total storage capacity into multiple smaller cells stacked vertically. Each cell's footprint is optimized to match its CMOS device, eliminating wasted space while achieving high density through vertical stacking of multiple cells.
3Quantity of substance
If the substrate area of the memory array device is increased to accommodate more memory layers, then the storage capacity is improved, but the area mismatch with the CMOS device is worsened, causing idle utilization space
Solution Approach 1:
The invention segments the memory system into standardized memory cells where each cell's memory array device has a substrate area specifically designed to match its CMOS device. This segmentation creates modular units that are easy to manufacture and assemble. The area matching is built into each cell's design, eliminating the need for complex area coordination and reducing idle space while maintaining high storage capacity through vertical stacking of multiple matched cells.
Data Source
AI summary
The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, and a three-dimensional memory. The three-dimensional memory device includes a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each memory cell includes a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, and the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device. The second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device facing away from the memory array device and electrically connected with the CMOS device. The memory array device of the first memory cell is bonded with the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the adjacent second memory cell.