3D NAND Memory Array Structure for Reduced Capacitive Coupling
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Solution Overview
Problem
Existing memory cell designs and array architectures, particularly in NAND memory arrays, face challenges in optimizing the structure and fabrication processes to enhance performance and efficiency.
Innovation Solution
The development of memory arrays with low-density silicon dioxide wrapping around wordline ends, incorporating charge-blocking regions of silicon oxynitride and silicon dioxide, and vertically-stacked memory cells with voids between adjacent cells, along with specific fabrication methods involving selective etching and oxidation processes to form charge-blocking and charge-storage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are used to increase storage density, then storage capacity is improved, but capacitive coupling between adjacent cells increases causing interference
Solution Approach 1:
The patent introduces charge-blocking regions as intermediary structures between vertically-stacked memory cells. These regions act as mediators that prevent direct capacitive coupling between adjacent cells while maintaining the vertical stacking architecture for high storage density. The charge-blocking regions are positioned at strategic locations where capacitive interference would otherwise occur, effectively isolating adjacent cells electrically.
Solution Approach 2:
The patent applies local quality by creating charge-blocking regions with specific material compositions (different dielectric constants) at particular locations within the memory cell structure. Rather than uniformly modifying the entire structure, the charge-blocking regions are selectively placed where needed to prevent capacitive coupling, allowing different parts of the structure to have different electrical properties optimized for their specific functions.
2Manufacturing precision
If conventional fabrication processes are used for memory arrays, then manufacturing simplicity is maintained, but structural precision and reliability of charge-storage regions are insufficient
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming charge-blocking regions first, then forming charge-storage regions in the gaps between them. This segmentation allows each region to be precisely controlled and formed with appropriate materials and dimensions, achieving high structural precision. The multi-stage process separates complex tasks into manageable steps, each optimized for specific requirements.
Solution Approach 2:
The charge-blocking regions are formed in advance before the charge-storage regions. This preliminary action establishes a precise template structure that guides subsequent formation of charge-storage regions. By preparing the charge-blocking regions first, the patent ensures that the final structure achieves the required precision without requiring complex simultaneous formation processes.
3Reliability
If charge-storage regions are formed without charge-blocking regions, then fabrication simplicity is maintained, but reliability and operational efficiency of memory cells deteriorate
Solution Approach 1:
The patent extracts and separates the charge-blocking function from the charge-storage function into distinct regions. By taking out the charge-blocking regions as separate entities formed in the gaps between charge-storage regions, the patent achieves better reliability through functional separation. This extraction allows each region to be optimized for its specific purpose while maintaining a relatively simple overall fabrication approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the structural integrity and operational efficiency of memory cells, reducing capacitive coupling and enhancing the reliability and performance of NAND memory arrays.
Implementation Method 1
low-density silicon dioxide wrapping around ends of wordline levels... reducing capacitive coupling
Implementation Method 2
oxidize the silicon nitride segments and to oxidize the spacing structures
Data Source
AI summary
Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.