3D NAND Memory Array Layout for Direct String-to-Tier Coupling
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Solution Overview
Problem
Existing memory array architectures face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architectures, which affect data retention and access speeds.
Innovation Solution
A method involving 'gate-last' or 'replacement-gate' processing is employed to form memory arrays, where conductive and insulative tiers are alternately stacked, with channel openings and trenches formed to create vertically-aligned memory cell strings, and conductive materials are used to establish direct electrical coupling between channel material and conductor tiers, ensuring robust connections and isolation between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory array architectures are used, then manufacturing processes are simpler, but structural integrity and electrical connectivity of vertically-stacked memory cells are compromised
Solution Approach 1:
The patent applies preliminary action by forming conductive and insulative tiers alternately stacked before forming channel openings and trenches. This preliminary stacking establishes a robust structural framework that ensures structural integrity and electrical connectivity are built into the architecture from the ground up, rather than attempting to fix connectivity issues later in the manufacturing process.
Solution Approach 2:
The patent segments the memory array into distinct conductive tiers and insulative tiers that are alternately stacked. This segmentation allows each tier to be optimized for its specific function (conduction or isolation) while maintaining overall structural integrity. The channel openings and trenches further segment the structure to create vertically-aligned memory cell strings with reliable electrical connections.
2Reliability
If vertically-stacked memory cells are formed without gate-last processing, then manufacturing is easier, but electrical connectivity and data retention are degraded
Solution Approach 1:
The patent applies the inversion principle by using gate-last or replacement-gate processing, where the gate structure is formed after the channel material and memory cell structure are already in place. This reverses the conventional approach and allows for optimized electrical connectivity and data retention, as the gate can be precisely positioned and tuned after the vertical stacking is complete.
Solution Approach 2:
The patent uses conductive materials as intermediaries to establish direct electrical coupling between the channel material and conductor tiers. This intermediary conductive layer ensures reliable electrical connectivity without requiring complex direct bonding processes, thus maintaining ease of manufacture while achieving improved data retention and access speeds.
3Reliability
If direct electrical coupling is established between channel material and conductor tiers, then electrical connectivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the conductive tiers and insulative tiers into a unified alternately stacked structure that is formed simultaneously through the same manufacturing processes. This merging approach ensures that all tiers are inherently aligned with each other, eliminating the need for high-precision alignment between separately formed components. The direct electrical coupling is achieved through this integrated structure rather than through complex multi-step alignment processes.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.