NAND Memory Array Segmentation via Dummy Word Lines
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Solution Overview
Problem
Increasing the number of memory cells per NAND string in NAND-type nonvolatile memory devices leads to a less flexible file system due to the need for erase operations in units of entire arrays, resulting in coarser granularity and decreased efficiency.
Innovation Solution
Incorporating dummy transistors and dummy word lines that divide the memory cell array into multiple blocks, allowing for independent erase operations and applying a coupling inhibition voltage to prevent disturbance between blocks during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells per NAND string is increased to improve integration density, then data storage capacity per chip area increases, but erase operation granularity becomes coarser and file system efficiency decreases
Solution Approach 1:
The patent introduces dummy transistors and dummy word lines to divide the memory cell array into multiple independent blocks. This segmentation allows erase operations to be performed on individual blocks rather than requiring erasure of entire arrays, thereby maintaining fine erase granularity even when each NAND string contains a large number of memory cells. The dummy structures create electrical isolation between blocks, enabling selective erasure of only the required block while preserving data in other blocks.
2Quantity of substance
If more memory cell transistors are added to each NAND string to increase integration density, then the proportion of control elements decreases, but the ability to perform selective erase operations deteriorates
Solution Approach 1:
By inserting dummy transistors at strategic positions within NAND strings and associated dummy word lines, the patent creates electrically isolated segments (blocks) within the memory array. This allows the system to maintain high memory cell density while enabling selective erase operations on individual blocks, as each block can be independently addressed and erased without affecting other blocks.
Solution Approach 2:
The dummy transistors and dummy word lines act as intermediary elements that provide electrical isolation between adjacent blocks. These intermediary structures prevent charge coupling and interference between blocks during erase operations, enabling precise control over which blocks are erased while maintaining high integration density.
3Measurement precision
If dummy transistors are introduced to divide the memory cell array into blocks, then erase operation precision improves, but device complexity increases
Solution Approach 1:
The patent employs dummy transistors and dummy word lines to segment the memory array into blocks, achieving precise erase control. While this increases structural complexity, the dummy elements are integrated into the existing NAND string architecture and can be formed using similar fabrication processes, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The patent optimizes the positioning and spacing of dummy transistors to achieve effective block isolation with minimal additional structures. By carefully controlling the electrical parameters and physical dimensions of the dummy elements, the patent achieves precise erase granularity while minimizing the increase in device complexity and maintaining compatibility with existing fabrication processes.
Data Source
AI summary
A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.