3D NAND Memory Array Layout for Selective Etching Control

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Solution Overview

Problem

In the formation of memory arrays, particularly in NAND architecture, the existing methods face challenges in achieving precise control over the etching process, which can lead to undesired etching of conductor material when sacrificial material is of the same etchable composition, resulting in inefficiencies and potential damage to the structure.

Innovation Solution

The method involves forming horizontally-elongated lines of different composition in the conductor tier between laterally-spaced memory-block regions, using metal material, and then forming a stack with alternating insulative and conductive tiers, where channel-material strings extend through these tiers, with conductive material electrically coupling the channel material to the conductor tier, and intervening insulating material providing isolation between memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If sacrificial material and conductor material are of the same etchable composition, then manufacturing simplicity is improved, but etching precision deteriorates leading to undesired etching of conductor material

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidetching precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the conductor material have a different etchable composition than the sacrificial material in specific regions. The conductor tier includes first conductor material in memory block regions and second conductor material in non-memory block regions, where these materials have different etchable compositions to enable selective etching while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the etchable composition parameter of the conductor material to resolve the contradiction. By adjusting the composition of the second conductor material in non-memory block regions to differ from the sacrificial material's composition, the etching process can selectively remove sacrificial material without damaging conductor material, thus improving etching precision.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If horizontally-elongated lines are formed in conductor tier before stack formation, then structural control is improved, but process complexity increases

Engineering Contradiction:
Improvestructural controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the horizontally-elongated lines of different composition in the conductor tier before forming the stack structure. This preliminary formation of conductive lines with controlled composition enables subsequent selective etching and precise structural definition during stack formation, improving overall manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conductor tier is segmented into different regions with different conductor material compositions - first conductor material in memory block regions and second conductor material in non-memory block regions. This segmentation allows differential etching behavior and provides precise structural control during subsequent processing steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11856764B2Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
Publication Date: 2023.12.26 LODESTAR LICENSING GROUP LLC
  • US11856764B2 patent drawing
  • US11856764B2 patent drawing
  • US11856764B2 patent drawing

AI summary

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.