NAND Array Parallel Transistor Two-Terminal Switching Device
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Solution Overview
Problem
Conventional NAND memory technologies face challenges with slow read speeds, increased bit error rates, and reduced memory cycling as they scale down past 25 nanometers, leading to inefficiencies and reliability issues due to high capacitive coupling and structural limitations.
Innovation Solution
A two-terminal memory-based NAND architecture with a 1 transistor-1 two-terminal memory device (1T-1D) arrangement, where memory cells are connected in series, allowing for faster write and erase times, improved data longevity, and reduced bit errors, utilizing resistive memory devices or other multi-state components to minimize capacitance and enhance read times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional NAND memory technology is used, then memory capacity can be increased through scaling, but read speed deteriorates and becomes slow
Solution Approach 1:
The patent changes the fundamental parameter of the memory cell structure from conventional three-terminal transistors to two-terminal switching devices. This structural parameter change enables faster switching speeds and improved read performance while reducing bit error rates, directly resolving the contradiction between speed and reliability in scaled NAND memory
2Quantity of substance
If memory density is increased through scaling below 25 nanometers, then more memory cells fit on chip, but capacitive coupling increases causing reliability issues
Solution Approach 1:
The patent extracts and eliminates the gate terminal from the conventional three-terminal transistor structure, replacing it with a two-terminal switching device. This extraction removes the source of capacitive coupling that causes bit errors, allowing high-density scaling below 25 nanometers to proceed without the reliability degradation that normally accompanies increased memory density
3Productivity
If conventional three-terminal transistors are used, then memory architecture is well-established, but write and erase times are slow
Solution Approach 1:
The patent changes the operational parameters of the memory cell by replacing three-terminal transistors with two-terminal switching devices. This structural parameter change enables significantly faster write and erase operations, improving productivity while reducing the time loss associated with conventional access methods in scaled NAND memory
Data Source
AI summary
Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.