3D NAND Memory Array Structure for Lower Wordline Coupling
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Solution Overview
Problem
Existing memory cell designs and array architectures, particularly in NAND memory arrays, face challenges in optimizing the structure and fabrication methods to enhance performance and efficiency.
Innovation Solution
The development of memory arrays with low-density silicon dioxide wrapping around wordline ends, incorporating silicon oxynitride as a charge-blocking region, and silicon oxynitride as a charge-trapping material, and the use of vertically-stacked memory cells with voids between adjacent cells, along with specific fabrication methods involving selective etching and oxidation processes to form charge-blocking regions and charge-trapping layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell structures are used with continuous dielectric layers, then manufacturing is simpler, but capacitive coupling between adjacent wordlines increases reducing performance
Solution Approach 1:
The continuous dielectric layer is segmented into discrete insulative liner regions positioned at specific locations between vertically-adjacent memory cell structures. This segmentation breaks the continuous path for capacitive coupling while maintaining structural integrity and enabling selective placement of insulative material where it is most needed to reduce interference between adjacent wordlines.
Solution Approach 2:
Insulative liner regions are introduced as intermediary elements between the conductive wordline structures. These liners act as mediators that electrically isolate adjacent memory cell structures, reducing parasitic capacitive coupling without requiring complete redesign of the memory cell architecture. The liners are positioned to specifically target and reduce unwanted electrical interaction between adjacent cells.
2Quantity of substance
If charge-storage material is continuously deposited along the opening, then charge storage capacity is maximized, but control over charge-blocking region formation becomes difficult
Solution Approach 1:
The tunneling material and charge-storage material are deposited in a controlled sequence before final structure completion. The tunneling material is formed first to establish a baseline layer, followed by charge-storage material deposition. This preliminary sequencing allows subsequent selective removal processes to precisely define charge-blocking regions while ensuring adequate charge storage material remains in appropriate locations for maintaining storage capacity.
Solution Approach 2:
portions of the charge-storage material are selectively removed to form charge-blocking regions. This extraction process creates the necessary charge-blocking functionality in specific locations while preserving charge-storage material in other locations. The selective removal enables precise control over where charge blocking occurs, allowing independent optimization of both charge storage capacity and charge-blocking region integrity.
3Quantity of substance
If vertically-stacked memory cells are used to increase density, then storage capacity improves, but capacitive coupling between adjacent cells increases
Solution Approach 1:
The insulative liner regions convert the potentially harmful effect of close spacing between vertically-stacked memory cells into a benefit. By strategically placing insulative material at interfaces between adjacent cells, the design utilizes the close proximity for high density while simultaneously mitigating the capacitive coupling that would otherwise result from such close spacing. The harmful coupling effect is transformed into an opportunity for targeted isolation.
Solution Approach 2:
Insulative properties are applied locally at specific positions between adjacent memory cell structures rather than uniformly throughout the entire structure. The insulative liners are positioned precisely where capacitive coupling occurs between vertically-adjacent cells, providing targeted reduction of harmful effects while maintaining high density architecture. This local application of insulative material optimizes the balance between storage capacity and signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and efficiency of memory arrays by reducing capacitive coupling between wordlines and improving the integrity of memory cell structures, leading to improved data storage capabilities.
Implementation Method 1
a charge-blocking region comprising silicon oxynitride between the charge-storage region and the gate
Implementation Method 2
silicon oxynitride as a charge-trapping material
Implementation Method 3
low-density silicon dioxide wrapping around ends of wordline levels
Data Source
AI summary
Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.