NAND Integrated Assembly Layout for Low Cross-Talk Memory Cells
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Solution Overview
Problem
Current NAND memory architectures face challenges in reducing capacitive coupling and cross-talk between conductive structures, which affect the performance and reliability of memory cells.
Innovation Solution
Incorporating voids between conductive structures and using a method of forming integrated assemblies with alternating levels of different materials, where conductive structures are selectively grown to reduce capacitive coupling and enhance electrical separation, and a panel is formed to separate memory-block regions, thereby improving electrical performance and structural uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive structures are placed in close proximity to increase memory density, then productivity is improved, but capacitive coupling and cross-talk between conductive structures increase, worsening reliability
Solution Approach 1:
An intermediate material layer is introduced between adjacent conductive structures (wordlines and bitlines) to act as an electrical mediator. This intermediate layer has controlled conductivity that allows signal transmission while blocking parasitic capacitive coupling, thus enabling high memory density without sacrificing reliability. The intermediate layer serves as a buffer that maintains electrical isolation where needed while permitting signal flow where required.
Solution Approach 2:
The patent applies different material compositions and conductivity levels to different regions of the conductive structures. Specifically, certain portions of the conductive structures have modified local properties (such as doped regions or material composition changes) to create zones of varying electrical characteristics. This local quality variation allows the structure to simultaneously achieve high density and low cross-talk by optimizing electrical properties at specific locations rather than uniformly across the entire structure.
2Quantity of substance
If more conductive structures are added to increase memory capacity, then quantity of substance increases, but manufacturing complexity increases due to selective growth requirements
Solution Approach 1:
The patent prepares the substrate and underlying layers in advance with pre-defined patterns and materials that guide the subsequent selective growth process. By pre-forming templates, seed layers, or structural guides before the selective growth of conductive structures, the manufacturing process is simplified. The preliminary structures act as blueprints that automatically guide where and how conductive materials grow, reducing the complexity of controlling multiple conductive structures during fabrication.
3Area of stationary object
If conductive structures are closely spaced to reduce device area, then area is reduced, but structural integrity deteriorates due to increased stress and cracking
Solution Approach 1:
The patent modifies physical and chemical parameters of the conductive structures and surrounding materials to maintain structural integrity at high density. This includes changing material composition, thickness, doping concentration, or thermal expansion coefficients of the conductive structures and intermediate layers. By adjusting these parameters, the structure can accommodate close spacing without developing excessive stress or cracking, thus maintaining strength while minimizing area.
Data Source
AI summary
Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.