NAND Flash Bit Line Selecting Transistor Gate Discharge Circuit
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Solution Overview
Problem
The existing NAND flash memory bit line selecting circuit's low voltage transistors are prone to breakdown due to the floating gate voltage during erase operations, which can lead to time-dependent dielectric breakdown (TDDB) issues, as the gate voltage is not properly discharged when the P well voltage is reduced.
Innovation Solution
Incorporating a discharging path between the gate of the bit line selecting transistor and a reference potential, using a discharging transistor or diodes, to ensure the gate voltage is reduced below the TDDB threshold during the discharge period, preventing transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If low voltage transistors are used in the bit line selecting circuit to reduce arrangement area, then the memory size is minimized, but the transistors are prone to breakdown due to floating gate voltage during erase operations
Solution Approach 1:
A discharging transistor is introduced as an intermediary component between the bit line selecting transistor gate and the reference potential. This discharging transistor acts as a mediator that safely provides a discharge path for the gate voltage during erase operations, preventing the harmful floating voltage condition while maintaining the low voltage transistor structure.
Solution Approach 2:
The discharging transistor is activated in advance during the erase operation to establish a discharge path before the gate voltage can reach dangerous levels. By preliminarily setting up the discharge mechanism, the system prevents the accumulation of floating voltage that would otherwise cause TDDB breakdown.
2Strength
If the gate of the bit line selecting transistor is set to floating state during erase operation, then the transistor can withstand high voltage, but the gate voltage is not discharged when P well voltage is reduced causing TDDB
Solution Approach 1:
The gate connection is made dynamic rather than static. During erase operations, the discharging transistor is activated to provide a discharge path, while during normal operations, the gate can be left floating to withstand high voltages. This dynamic switching of the gate's electrical state allows the system to adapt to different operational requirements.
Solution Approach 2:
The discharging transistor ensures continuous monitoring and discharge of the gate voltage during the erase operation. By maintaining an active discharge path throughout the critical voltage transition period, the system continuously prevents the buildup of harmful voltage differences that could lead to gate oxide breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents transistor breakdown by ensuring the gate voltage of the bit line selecting transistors is discharged in sync with the P well voltage, thereby inhibiting TDDB and maintaining the integrity of the memory device.
Implementation Method 1
Incorporating a discharging path between the gate of the bit line selecting transistor and a reference potential, using a discharging transistor or diodes, to ensure the gate voltage is reduced below the TDDB threshold during the discharge period
Data Source
AI summary
A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.