NAND Memory Read Calibration Using Valley Voltage and Bit Flips
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Solution Overview
Problem
The accuracy of reading data stored in NAND memory cells is affected by charge fluctuations due to increased use time and temperature variations, leading to bit flips and data integrity issues.
Innovation Solution
A memory device and system that includes a peripheral circuit to adjust read voltages iteratively, determining a valley voltage for accurate data reading by analyzing bit flips, and employing error correction codes to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If read operations are performed on NAND memory cells over time, then data storage capacity is maintained, but charge stored in memory cells changes due to use time and temperature variations, affecting reading accuracy
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the read voltage based on the number of program/erase cycles and temperature conditions. The memory device monitors usage parameters and modifies the read voltage parameter to compensate for charge fluctuations, thereby maintaining reading accuracy over extended storage duration and varying environmental conditions.
2Measurement precision
If the read voltage is adjusted to compensate for charge fluctuations, then reading accuracy is improved, but additional voltage adjustment operations increase processing time
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing optimal read voltage values corresponding to different program/erase cycle counts and temperature ranges. When a read operation is initiated, the device quickly retrieves the appropriate voltage from lookup tables based on monitored parameters, avoiding time-consuming real-time calculations while maintaining high reading accuracy.
3Reliability
If error correction codes are employed to ensure data integrity, then data reliability is improved, but computational complexity and processing overhead increase
Solution Approach 1:
The patent uses error correction codes as an intermediary mechanism between the memory cells and the data processing system. The ECC system detects and corrects bit flips caused by charge fluctuations, acting as a buffer that protects data integrity without requiring fundamental changes to the memory cell structure or operation, thus managing complexity through a specialized correction layer.
Data Source
AI summary
An example of the present application discloses a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; perform multiple adjustments to the initial target read voltage, and obtain the first result corresponding to the target location at the target read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a plurality of the obtained first results.