3D NAND Bit Line Layout to Reduce Signal Delay and Wiring Congestion
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Solution Overview
Problem
Conventional NAND-type flash memories with three-dimensionally arranged memory cells face challenges in achieving high operation speed due to signal delay in bit lines and wiring congestion in the lower part of the memory cell array.
Innovation Solution
The semiconductor storage device employs a one-side sense amplifier system with the memory cell array divided into regions to distribute lead-in openings for bit lines, reducing wiring congestion and shortening the length of lower bit lines, thereby enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged in NAND-type flash memory, then storage capacity is increased, but signal delay in bit lines increases and operation speed decreases
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block containing a subset of memory cells connected to bit lines. This segmentation reduces the number of memory cells per bit line, thereby reducing signal delay and improving operation speed while maintaining total storage capacity through increased block count
Solution Approach 2:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking, where memory cells are arranged in multiple layers vertically. This allows increased storage capacity without proportionally increasing bit line length, as cells in different layers can share the same bit line structure
2Adaptability or versatility
If bit lines are extended to cover the entire memory cell array, then all memory cells can be accessed, but wiring congestion increases in the lower part of the array
Solution Approach 1:
The memory cell array is divided into multiple blocks, each with its own subset of bit lines. This segmentation allows bit lines to be shorter and fewer in number within each block, reducing wiring congestion in the lower part of the array while still providing access to all memory cells through the block structure
Solution Approach 2:
Word lines are used to pre-select specific memory cells within blocks before bit lines are activated for data access. This preliminary selection reduces the number of active bit lines at any given time, thereby reducing wiring congestion and interference
Data Source
AI summary
A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.