NAND Memory Bit Line Control for Faster Low-Current Page Reads
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Solution Overview
Problem
Current NAND flash memory devices face challenges in efficiently managing bit line operations for read operations, particularly in reducing operation time and current consumption during 8 KB page reads without increasing the number of select gate lines, which can slow down read speeds.
Innovation Solution
The memory device employs select transistors with flag data written in 'LS' and 'HS' states to control bit line states, allowing for independent control of even and odd bit lines, thereby reducing apparent capacitance and current consumption during 8 KB page reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of select gate lines is increased to control more bit lines independently, then the control precision over bit line states improves, but the read speed deteriorates due to increased operation time
Solution Approach 1:
The patent segments the bit lines into even and odd groups, using flag data in select transistors to independently control each group. This segmentation allows precise control of bit line states without requiring additional select gate lines, thus maintaining read speed while improving control precision.
Solution Approach 2:
The patent uses flag data (LS/HS states) stored in select transistors to change the control parameters of bit lines. By reading flag data and controlling select transistors accordingly, the system can set bit lines to different states (connected, floating, or grounded) without adding physical select gate lines, resolving the contradiction between control precision and read speed.
2Adaptability or versatility
If the number of select gate lines is increased to manage bit line operations, then the control capability improves, but the device complexity increases
Solution Approach 1:
The select transistors serve multiple functions: they act as both memory cells for storing flag data and as control elements for managing bit line states. This multi-functionality eliminates the need for separate select gate lines, improving control capability while avoiding increased device complexity.
Solution Approach 2:
The flag data stored in the select transistors themselves is used to control the state of the same transistors during read operations. This self-service mechanism allows the memory structure to manage its own bit line control without requiring external select gate lines, enhancing adaptability while maintaining simple device architecture.
3Productivity
If all bit lines are actively driven during read operations, then the data access completeness improves, but the current consumption increases
Solution Approach 1:
Instead of actively driving all bit lines during every read operation, the patent uses flag data to determine which bit lines need to be accessed. By controlling select transistors based on flag data, only necessary bit lines are activated, ensuring data access completeness while reducing current consumption through partial action.
Solution Approach 2:
The patent implements periodic control of bit line states by reading flag data and adjusting select transistor configurations accordingly. This periodic action allows the system to switch between different bit line activation patterns (even/odd groups) based on data access requirements, optimizing both productivity and energy efficiency.
Data Source
AI summary
A memory device according to one embodiment includes includes bit lines, strings, first and second wirings, a word line, and a sequencer. Each of the strings has one end coupled to the bit lines. Each of the strings includes a memory cell, and first and second transistors coupled in series. The first wiring is coupled to the first transistor of each of the strings. The second wiring is coupled to the second transistor of each of the strings. The word line is coupled to the memory cell of each of the strings. The sequencer is configured to, in a read operation of N bytes in which the word line is selected, apply a first voltage to one of the first wiring line and the second wiring line, and apply a second voltage higher than the first voltage to the other of the first wiring line and the second wiring line.