3D NAND Bit Line Layout With One-Side Sense Amplifiers
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Solution Overview
Problem
Conventional NAND-type flash memories with three-dimensionally arranged memory cells face challenges in achieving high operation speed due to signal delay in bit lines and wiring congestion in the lower part of the memory cell array.
Innovation Solution
The semiconductor storage device employs a one-side sense amplifier system where the memory cell array is divided into regions to distribute lead-in openings for bit lines, reducing wiring congestion and shortening the length of lower bit lines, thereby enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged in NAND-type flash memory, then storage capacity is increased, but signal delay in bit lines increases and operation speed decreases
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block containing a separate sense amplifier. This segmentation allows bit lines to be shorter within each block, reducing signal delay while maintaining high storage capacity through three-dimensional stacking. The patent implements this by creating independent read/write pathways for each block, preventing signal propagation delays from affecting the entire array.
2Adaptability or versatility
If bit lines are extended to cover the lower part of the memory cell array, then all memory cells can be accessed, but wiring congestion increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional bit line layout to a three-dimensional structure where bit lines are stacked in multiple layers. This allows vertical routing of bit lines above the memory cell array, eliminating the need for extensive wiring in the lower part of the array. The bit lines extend in the vertical dimension rather than horizontally congesting the lower region, thus maintaining full memory cell accessibility while reducing wiring congestion.
3Speed
If multiple wiring layers are used to route bit lines, then signal delay is reduced, but manufacturing cost increases
Solution Approach 1:
The memory array is divided into blocks with sense amplifiers positioned at different locations to serve specific blocks. This segmentation allows the use of fewer wiring layers because each sense amplifier only needs to connect to its local block's bit lines, rather than requiring global routing across the entire array. The reduced routing distance and localized connections decrease the number of wiring layers needed, lowering manufacturing complexity and cost.
Data Source
AI summary
A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.