NAND Flash Memory Bitline Setup Circuit for Coupling Capacitance Reduction
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Solution Overview
Problem
NAND flash memory devices face program failures due to coupling capacitance issues, leading to un-programmed memory cells, which are exacerbated by increasing program voltage in multiple loops, causing over-programming and unexpected results.
Innovation Solution
A NAND flash memory device with a bitline setup circuit that sequentially discharges bitlines based on input data, reducing coupling capacitance by dividing bitlines into multiple groups and using a two-stage bitline setup technique to establish voltages for programming, thereby preventing voltage drops and ensuring accurate programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple program loops with increasing program voltage are used to program memory cells, then program failures due to coupling capacitance are addressed, but over-programming occurs and unexpected results are produced
Solution Approach 1:
The bitline setup circuit divides the bitline discharge operation into multiple discrete stages, with each stage discharging a specific group of bitlines based on the input data. This segmentation allows precise control over which bitlines are discharged and when, preventing the over-programming that occurs with traditional multi-loop voltage increases while still addressing coupling capacitance issues.
Solution Approach 2:
The bitline setup circuit performs preliminary discharge of selected bitlines before the actual programming operation begins. By pre-establishing the voltage state of bitlines according to the input data, the circuit eliminates the need for multiple program loops with increasing voltages, thereby preventing over-programming while ensuring reliable programming.
2Ease of operation
If simultaneous discharge of all bitlines is performed, then programming operation is simplified, but coupling capacitance causes voltage drops leading to program failures
Solution Approach 1:
Instead of simultaneously discharging all bitlines, the bitline setup circuit segments the discharge operation into multiple groups. Each group of bitlines is discharged in a separate stage controlled by the bitline setup circuit, reducing coupling capacitance effects while maintaining operational simplicity through automated control.
Solution Approach 2:
The bitline setup circuit dynamically controls the discharge timing of different bitline groups based on the input data requirements. This dynamic approach allows the circuit to adapt the discharge sequence to minimize coupling capacitance effects while maintaining ease of operation through automated timing control.
Data Source
AI summary
Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.