NAND Bitline Voltage Boosting via Parasitic Capacitance
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Solution Overview
Problem
Existing methods for programming NAND memory devices require additional silicon area and increased time due to the need for charge pump generators to inhibit unprogrammed cells, as capacitive coupling between bitlines can lead to unintended programming of adjacent cells.
Innovation Solution
The method exploits parasitic capacitances between adjacent bitlines to boost the voltage of unprogrammed bitlines, allowing them to be inhibited from programming without dedicated charge pump generators, by biasing even or odd bitlines with a supply voltage and grounding or grounding the adjacent bitlines, thereby increasing the bias voltage through coupling capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge pump generators are added to boost bitline voltages for inhibiting unprogrammed cells, then programming reliability is improved, but device area and complexity increase
Solution Approach 1:
The patent converts the harmful parasitic capacitance between adjacent bitlines into a beneficial voltage boosting mechanism. By intentionally grounding alternating bitlines (e.g., even bitlines) during programming operations, the capacitive coupling from adjacent charged bitlines (e.g., odd bitlines) automatically boosts the voltage of grounded bitlines to inhibition levels, eliminating the need for dedicated charge pump circuits while preventing unintended programming of unselected cells
2Manufacturing precision
If charge pump generators are used to inhibit unprogrammed cells, then programming accuracy is improved, but manufacturing cost and area increase
Solution Approach 1:
The patent implements a self-service mechanism where the programming operation itself generates the necessary inhibition voltage through capacitive coupling. The act of charging selected bitlines for programming automatically induces sufficient voltage on adjacent grounded bitlines through parasitic capacitance, creating a self-regulating system that prevents programming of unselected cells without requiring additional active components or complex control circuitry
3Device complexity
If conventional programming methods are used without exploiting parasitic capacitance, then device structure is simpler, but unintended programming of adjacent cells occurs
Solution Approach 1:
The patent applies preliminary action by pre-charging alternating bitlines (e.g., odd bitlines) to the programming voltage before the actual programming pulse is applied to selected cells. This preliminary charging of adjacent bitlines creates the necessary electric field through parasitic capacitance that will automatically inhibit any unintended programming during the subsequent programming operation, ensuring programming integrity from the outset
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents unintended programming operations without the need for additional charge pump generators or increased programming time, effectively utilizing capacitive coupling to maintain the integrity of programming operations in NAND memory devices.
Implementation Method 1
The method exploits parasitic capacitances between adjacent bitlines to boost the voltage of unprogrammed bitlines, allowing them to be inhibited from programming without dedicated charge pump generators
Implementation Method 2
by biasing even or odd bitlines with a supply voltage and grounding or grounding the adjacent bitlines, thereby increasing the bias voltage through coupling capacitances
Data Source
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AI summary
The capacitive coupling between two adjacent bitlines of a NAND memory device is relevant and this may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. According to the disclosed method, first the even (odd) bitlines that include cells not to be programmed (BLE<1>,...,BLE<n>) are biased with a first voltage for inhibiting them from being programmed, typically the supply voltage (VDD), while the even (odd) bitlines that include cells to be programmed are grounded. Successively, the adjacent odd (even) bitlines (BLO<0>,...,BLO<n>) are biased at the supply voltage (VDD) or at an auxiliary voltage, for boosting the bias voltage of the even (odd) bitlines above the supply voltage. With this expedient, the bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines. Therefore, no dedicated charge pump generator is needed.