3D NAND Memory Block Control for Partial Bad Block Utilization
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Solution Overview
Problem
In NAND flash memory devices, the inefficiency in using memory blocks due to partial bad blocks reduces storage capacity and increases circuit area, as existing technologies lack effective methods to independently control and utilize good and bad blocks within the same memory block, leading to decreased performance and increased operational time.
Innovation Solution
The memory device incorporates block decoders that can independently switch the states of transfer switches and select gate lines for partial blocks in different memory chips, allowing for the exclusion of bad blocks and efficient use of good blocks, thereby improving storage efficiency and reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing technologies are used to control memory blocks, then the memory device can store data, but the use efficiency of memory blocks is reduced due to partial bad blocks
Solution Approach 1:
The patent divides a memory block into multiple partial blocks (first partial block and second partial block) and provides independent control mechanisms for each partial block through separate block decoders. This segmentation allows the system to independently manage good and bad portions of a memory block, enabling continued use of functional partial blocks even when others are defective, thereby improving memory block utilization efficiency without sacrificing storage capacity.
2Productivity
If existing technologies are used to control memory blocks, then the memory device can store data, but the circuit area increases
Solution Approach 1:
The patent merges the control functions for multiple partial blocks into a single integrated block decoder structure that can independently control different partial blocks within the same memory block. By combining control capabilities for the first and second partial blocks in one decoder unit, the design achieves fine-grained control without proportionally increasing circuit area, thus improving memory block use efficiency while controlling the growth of circuit footprint.
3Productivity
If existing technologies are used to control memory blocks, then the memory device can store data, but the operation time increases
Solution Approach 1:
The patent implements dynamic control of partial blocks through block decoders that can independently switch between different partial blocks based on their operational status. This dynamic control mechanism allows the system to quickly identify and activate functional partial blocks while bypassing defective ones, reducing the time required for memory operations and improving overall productivity without requiring static allocation of entire memory blocks.
Data Source
AI summary
According to one embodiment, a memory device includes: a first chip including a first memory cell array; a second chip in contact with the first chip and including a second memory cell array; and a third chip in contact with the second chip and including a control circuit. The first memory cell array includes first and second transistors coupled in series. The second memory cell array includes third and fourth transistors coupled in series. The control circuit includes: fifth, sixth, and seventh transistors respectively having first ends coupled to gates of the first, third, and second and fourth transistors; a first decoder configured to switch a state of the fifth transistor; and a second decoder configured to switch a state of the sixth transistor independently of the state of the fifth transistor.