NAND Memory Block Mapping for Redundant Low-Latency Reads
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Solution Overview
Problem
Existing methods for storing data in NAND memory devices are inefficient due to the need to split data into sub-blocks and store error bits separately, leading to increased read overhead and latency as the number of NAND devices increases, resulting in reduced performance when reading large numbers of small blocks of data.
Innovation Solution
The method involves generating error checking data for multiple blocks of data and storing each block and its associated error checking data in physically distinct non-volatile memory devices, with a mapping system that links the blocks for efficient retrieval and error correction, allowing for independent read/write operations and reducing read latency by handling entire blocks rather than sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is split into sub-blocks and stored across multiple NAND devices with separate error bits, then data redundancy and error protection are improved, but read overhead and latency increase
Solution Approach 1:
The patent divides data into blocks and distributes them across multiple NAND devices, with each device storing a complete block rather than fragmented sub-blocks. This segmentation approach maintains data redundancy for error protection while reducing the complexity of read operations compared to storing sub-blocks across devices.
Solution Approach 2:
The patent combines error checking data with the data blocks themselves, storing both in the same NAND devices rather than separating them. This merging eliminates the need for separate error bit storage and reduces the number of devices that must be accessed during read operations, thereby reducing read latency while maintaining error protection.
2Quantity of substance
If data blocks are distributed across more NAND devices, then data capacity and redundancy are improved, but read overhead increases
Solution Approach 1:
The patent segments data into blocks and distributes them across multiple NAND devices to increase total storage capacity. Each device stores complete blocks rather than sub-blocks, which maintains organizational simplicity.
Solution Approach 2:
The patent merges error checking data with data blocks and stores them together in the same devices. This approach allows the system to scale across multiple devices for increased capacity while maintaining efficient read operations, as error checking can be performed locally without requiring additional device accesses.
3Productivity
If sub-blocks are stored in buffer until full block is assembled, then storage efficiency is improved, but data loss risk increases
Solution Approach 1:
The patent performs preliminary action by assembling complete blocks in non-volatile memory before they are fully received, rather than holding incomplete blocks in volatile buffer. This approach allows the system to achieve storage efficiency through immediate permanent storage while eliminating data loss risk associated with volatile buffer storage.
Solution Approach 2:
The patent avoids relying on volatile buffer memory by directly storing complete blocks in non-volatile memory devices. This eliminates the need for expensive error correction mechanisms that would be required to protect data held in volatile storage, while maintaining data safety through the inherent non-volatility of the storage medium.
Data Source
AI summary
A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.