NAND Memory Block Select Signal Control for Delayed Read Disturb
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Solution Overview
Problem
Non-volatile memory devices face challenges with delayed read disturb, where residual voltages on word lines after a read operation can affect memory cells, particularly those in an erase state, leading to increased bit error rates and data misreading.
Innovation Solution
The proposed solution involves discharging the unselected control gate bias to a lower voltage, such as VSS, before turning off the block select signal and then biasing it back to VDD−Vt/VCC−Vt after the block select signal transitions off, which helps in reducing residual potential on word lines and mitigating delayed read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the block select signal is turned off immediately after a read operation, then the read operation completes quickly, but residual voltages on word lines cause delayed read disturb affecting memory cells in erase state
Solution Approach 1:
The control circuit discharges the unselected control gate bias to a lower voltage level before turning off the block select signal. This preliminary discharge action removes residual voltages from word lines that would otherwise cause delayed read disturb, ensuring memory cells in erase state are protected while maintaining efficient read operation timing
2Stability of the object's composition
If the unselected control gate bias is maintained at a high level, then the memory cells remain in a stable state, but residual potential on word lines increases causing delayed read disturb
Solution Approach 1:
The control circuit dynamically adjusts the unselected control gate bias voltage in three distinct phases: maintaining it at a high level (VDD-Vt/VCC-Vt) during the read operation for proper memory cell operation, discharging it to a lower level before turning off the block select signal to eliminate residual voltages, and then re-biasing it back to the high level after the block select signal transitions off. This dynamic voltage adjustment resolves the contradiction between maintaining stability and preventing harmful residual effects
3Object-affected harmful factors
If the unselected control gate is discharged to a very low voltage, then residual potential on word lines is minimized reducing delayed read disturb, but additional voltage transitions increase operation complexity
Solution Approach 1:
The control circuit changes the voltage parameter of the unselected control gate bias through controlled transitions: maintaining it at VDD-Vt/VCC-Vt during reading, discharging it to a lower voltage (such as VSS or an intermediate level) before the block select signal turns off to minimize residual potential, and re-biasing it afterward. This parameter adjustment strategy effectively reduces delayed read disturb while managing operational complexity through systematic voltage control
Data Source
AI summary
An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A plurality of blocks are connected together and selected for operations using a block select signal. A control circuit is configured to, after a read operation of memory cells of the block, hold a block select signal applied to a block select line to select a group of blocks having a same block select line at an on level. The control circuit can further discharge an unselected control gate in the group of blocks from a charged level to a lower level, lower than charged, prior to turning off the block select signal and charge the unselected control gate to a level greater than the lower level after the block select signal transitions from the on level to an off level.