Multi-Wafer NAND Bonding With Separate Bit Lines for Parallel Scaling
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Solution Overview
Problem
Current memory devices face challenges in scaling and efficient operation due to the complexity of control circuitry and electrical connections between multiple semiconductor dies, leading to increased space occupation and reduced performance.
Innovation Solution
The integration of a control semiconductor die with multiple memory semiconductor dies using a separate bit line architecture and wafer-to-wafer bonding, along with through-silicon vias and Cu-to-Cu bonding techniques, allows for parallel memory operations and efficient scaling by reducing the size of bond pads and pitch, and using a hybrid bonding method to secure the dies together.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control circuitry is integrated on the same die as memory cells, then device complexity is reduced, but the control circuitry occupies substantial space on the semiconductor die
Solution Approach 1:
The patent divides the memory device into separate semiconductor dies: one die dedicated to control circuitry and another die dedicated to memory cells. This segmentation allows each die to be optimized for its specific function while reducing the total space required compared to integrating both on a single die.
2Productivity
If multiple semiconductor dies are bonded together, then memory capacity and parallel operation are improved, but the size of bond pads and pitch increase
Solution Approach 1:
The patent utilizes through-silicon vias to create vertical electrical connections between bonded semiconductor dies. This three-dimensional bonding approach allows multiple dies to be stacked and connected vertically, enabling parallel memory operations while minimizing the horizontal footprint of bond pads and pitch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables compact, efficient, and scalable memory devices with improved parallel operation capabilities, reducing the complexity of control circuitry and enhancing memory performance by minimizing electrical connection challenges.
Implementation Method 1
through-silicon vias and Cu-to-Cu bonding techniques, allows for parallel memory operations
Implementation Method 2
wafer-to-wafer bonding, along with through-silicon vias and Cu-to-Cu bonding techniques
Data Source
AI summary
Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.