3D NAND Substrate Bonding Layout for Warpage Control
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity, particularly in achieving high-capacity data storage systems, where existing methods often rely on two-dimensional memory cell arrangements, which limit storage density and efficiency.
Innovation Solution
The semiconductor device incorporates a first and second substrate structure with gate electrodes, channel structures, and dummy pattern layers made of insulating material, where the second metal bonding layers have a specific thickness and the dummy pattern layers are thicker, enhancing interconnection and reducing warpage, thereby improving bonding reliability and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory cell arrangements are used, then device complexity is reduced, but data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangements to three-dimensional stacked substrate structures. Multiple substrates are vertically stacked with interconnection structures extending between them, enabling data storage capacity expansion by utilizing the vertical dimension while maintaining manageable device complexity through modular architecture.
2Quantity of substance
If multiple substrates are stacked to increase storage capacity, then data storage capacity improves, but warpage increases reducing bonding reliability
Solution Approach 1:
The patent introduces dummy pattern layers with specific thickness parameters (second thickness greater than first thickness of metal bonding layers) to adjust stress distribution. By changing the geometric parameters of these dummy structures, warpage is controlled to remain within acceptable ranges, ensuring bonding reliability while maintaining high storage capacity through multi-substrate stacking.
Solution Approach 2:
Dummy pattern layers made of insulating materials serve as intermediary elements between metal bonding layers. These dummy structures act as stress mediators that compensate for thermal expansion differences and mechanical stress in the stacked substrate configuration, preventing warpage-induced bonding failures while enabling high-capacity data storage.
3Reliability
If dummy pattern layers with greater thickness are added, then warpage is reduced improving bonding reliability, but device complexity increases
Solution Approach 1:
The dummy pattern layers serve multiple functions simultaneously: they act as stress compensation structures to reduce warpage, provide mechanical support in the stacked configuration, and function as insulating elements between conductive layers. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving improved bonding reliability.
Data Source
AI summary
A semiconductor device includes a first substrate structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first metal bonding layers on the first interconnection structure; and a second substrate structure connected to the first substrate structure, and the second substrate structure includes: a plating layer; gate electrodes stacked and spaced apart from each other in a first direction below the plating layer; channel structures penetrating through the gate electrodes and extending in the first direction; a separation region penetrating through the gate electrodes and extending in a second direction; a second interconnection structure below the gate electrodes and the channel structures; second metal bonding layers below the second interconnection structure and connected to the first metal bonding layers; and dummy pattern layers between the second metal bonding layers, extending in the second direction, and including an insulating material.