NAND Die Bond Wire Segmentation for I/O Impedance Matching
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Solution Overview
Problem
Conventional bond wire architectures in NAND memory devices suffer from impedance mismatch issues, leading to restricted bandwidth in I/O channels, which limits data transmission efficiency.
Innovation Solution
The introduction of intermediate conductor segments or bond wire segments of specific lengths and configurations between pin caps within memory dies to increase impedance and enhance bandwidth, by forming additional inductance in the I/O channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bond wire architecture is used to connect substrate to memory dies, then the structure is simple and easy to manufacture, but the bandwidth is restricted due to impedance mismatch
Solution Approach 1:
The bond wire connection is segmented into multiple sections: a first bond wire section connecting the substrate to a first pin cap, and a second bond wire section connecting the first pin cap to a second pin cap on the memory die. This segmentation allows different impedance characteristics in different sections to optimize both manufacturability and bandwidth performance.
Solution Approach 2:
The first pin cap on the memory die serves as an intermediary element between the substrate and the second pin cap. This intermediate connection point enables impedance transformation and matching, resolving the bandwidth limitation caused by direct bond wire connection while maintaining manufacturing simplicity.
2Speed
If bond wire segments of specific lengths are introduced to increase impedance, then the bandwidth increases from 2 GHz to 13 GHz, but the device complexity increases
Solution Approach 1:
Specific length parameters are assigned to bond wire segments to achieve desired impedance characteristics. The first bond wire section has a first length and the second bond wire section has a second length, where these length parameters are optimized to transform impedance and increase bandwidth from 2 GHz to 13 GHz while controlling complexity.
3Speed
If multiple pin caps are used on memory die for intermediate connections, then the impedance matching improves and bandwidth increases, but the manufacturing complexity increases
Solution Approach 1:
The first pin cap on the memory die serves multiple functions: it acts as an electrical connection point for the first bond wire section, serves as an intermediary for impedance transformation, and provides a mounting point for the second bond wire section. This multi-functionality enables bandwidth improvement without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the bandwidth of I/O channels from 2 GHz to 13 GHz by adding impedance, thereby improving data transmission efficiency across multiple memory dies in a package.
Implementation Method 1
a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die... by forming additional inductance in the I/O channels
Data Source
AI summary
A storage device includes a substrate of a memory package that includes a first pin pad, a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel, and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.