NAND Boot Code Placement for Timeout-Sensitive Initialization
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Solution Overview
Problem
Accessing data in multiple-level memory cells in NAND devices is slower and more power-consuming, leading to increased latency and error correction procedures, which can cause initialization timeouts and failures in host systems, especially during boot-up sequences.
Innovation Solution
Dynamically store initialization code in specific portions of the memory system based on indicated timeout durations and power thresholds, utilizing high-reliability memory cells to reduce the likelihood of exceeding these limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in multiple-level memory cells to increase storage capacity, then storage density is improved, but access speed and power consumption worsen
Solution Approach 1:
The patent segments the boot sequence into multiple portions and stores them in different memory cell types (SLC and MLC). Critical time-sensitive portions are stored in fast SLC cells, while less time-critical portions are stored in higher-capacity MLC cells. This segmentation resolves the contradiction by allowing the system to utilize both high-capacity MLC storage and fast SLC access where needed.
Solution Approach 2:
The patent applies local quality by assigning different memory cell characteristics to different portions of the boot sequence based on their specific requirements. Time-sensitive boot portions receive the quality attribute of fast access (SLC), while other portions utilize high capacity (MLC). This localized optimization resolves the contradiction by matching memory characteristics to specific functional requirements rather than using a uniform storage approach.
2Quantity of substance
If data is stored in multiple-level memory cells to increase storage capacity, then storage density is improved, but power consumption worsens
Solution Approach 1:
The patent segments the boot sequence storage across different memory cell types, storing only critical portions in power-intensive SLC cells while keeping other portions in more power-efficient MLC cells. This segmentation resolves the power consumption contradiction by minimizing the amount of data stored in high-power SLC memory while maintaining overall system functionality.
Solution Approach 2:
The patent applies local quality by assigning different power characteristics to different boot sequence portions based on their criticality. Time-sensitive portions are localized to SLC with higher power consumption, while less critical portions use MLC with lower power consumption. This resolves the power contradiction by optimizing power usage for each specific functional requirement rather than uniformly across all boot data.
3Reliability
If error correction procedures are performed to handle increased errors in multiple-level cells, then reliability is improved, but initialization time worsens
Solution Approach 1:
The patent segments the boot sequence into portions stored in SLC and MLC cells, leveraging the inherent reliability of SLC for critical portions without requiring extensive error correction. This segmentation resolves the contradiction by placing time-sensitive, reliability-critical data in SLC which has lower error rates, thereby reducing the need for error correction procedures and associated time losses.
4Quantity of substance
If initialization code is stored in multiple-level cells to utilize high capacity, then storage efficiency is improved, but timeout occurrence worsens
Solution Approach 1:
The patent segments the initialization code across SLC and MLC portions, storing time-critical code segments in fast SLC cells and less time-sensitive segments in higher-capacity MLC cells. This segmentation resolves the timeout contradiction by ensuring that critical initialization operations complete within timeout thresholds using SLC speed, while still utilizing MLC capacity for overall storage efficiency.
Solution Approach 2:
The patent applies local quality by assigning different performance characteristics to different portions of the initialization code based on their timeout sensitivity. Critical portions are localized to SLC with guaranteed fast access, while non-critical portions use MLC with higher capacity. This resolves the timeout contradiction by matching local memory characteristics to the specific timing requirements of each code portion.
Data Source
AI summary
Methods, systems, and devices for determining locations in not-and (NAND) memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence are received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells are selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.