NAND Memory Conductor Bridge Layout for Uniform Layer Resistance
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Solution Overview
Problem
Existing semiconductor storage devices face performance deterioration due to significant differences in electrical resistance values between conductor layers, leading to voltage delays and increased power consumption, particularly in NAND type flash memory devices.
Innovation Solution
The semiconductor storage device is designed with a specific configuration of stacked regions and bridge portions that reduce electrical resistance by optimizing the connection between conductor layers, ensuring uniform electrical resistance values across all layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conductor layers are connected in a stair-stepped structure to enable individual voltage application, then ease of operation is improved, but electrical resistance differences between layers increase causing voltage delays and power consumption issues
Solution Approach 1:
The patent applies equipotentiality by introducing bridge portions that electrically connect conductor layers at different positions, ensuring they reach the same voltage level simultaneously. The bridge portions are positioned and dimensioned to balance the electrical resistance paths, so that voltage applied to different conductor layers arrives at comparable times, eliminating voltage delays and reducing power consumption while maintaining the ability to individually control each layer.
2Ease of operation
If conductor layers are formed in stair-stepped structure for connection to contacts, then ease of operation is improved, but device complexity increases due to additional bridge portions
Solution Approach 1:
The patent merges the bridge portions with the existing stair-stepped conductor layer structure, where the bridge portions are integrated into the same formation process and spatial arrangement. This combining approach allows the bridge portions to serve dual purposes: providing necessary electrical connections while maintaining the stair-stepped configuration for contact access, thereby reducing overall structural complexity rather than increasing it.
Data Source
AI summary
A semiconductor storage device includes a first stacked region, a second stacked region, and a connection region arranged between the first and second stacked regions. In the connection region, one of a plurality of conductor layers in an upper stepped portion is connected to one of the plurality of conductor layers in the first stacked region via one of the plurality of conductor layers in a bridge portion.