NAND Write-Path Buffer Allocation via Data Chopping
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Solution Overview
Problem
NAND flash memory systems face inefficiencies in buffer allocation, leading to high area occupancy and power consumption due to slow interface throughput and large page sizes, which hinder overall system performance.
Innovation Solution
Implementing an efficient write-path system that chops user data into smaller units using a chopping factor, reducing buffer sizes and optimizing power consumption by distributing data across multiple NAND channels in parallel, thereby reducing area usage and static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional buffer allocation is used for NAND write-path, then data transfer capability is maintained, but buffer area occupancy and power consumption increase
Solution Approach 1:
The patent divides the buffer memory into multiple channels, with each channel having its own dedicated buffer. This segmentation allows the system to allocate buffer resources more efficiently by distributing data across multiple smaller buffers rather than using a single large buffer, thereby reducing total buffer area while maintaining data transfer capability.
Solution Approach 2:
The patent introduces a channel dimension to the buffer allocation strategy by organizing buffers in a multi-channel architecture. Instead of allocating buffer space in a single dimension, the system distributes data across multiple channels, each with its own buffer, effectively adding a spatial dimension to resource allocation and reducing the area required per buffer.
2Use of energy by stationary object
If traditional buffer allocation is used for NAND write-path, then data transfer capability is maintained, but power consumption increases
Solution Approach 1:
By segmenting the buffer into multiple channels with smaller individual buffers, the system reduces the total power consumption. Each smaller buffer requires less power to maintain, and the distributed architecture allows for more efficient power management across the write-path system while preserving overall data transfer capability.
Solution Approach 2:
The patent changes the buffer allocation parameters by transitioning from a single large buffer to multiple smaller buffers across different channels. This parameter change optimizes the power-area-product metric by reducing the total buffer area and associated static power consumption while maintaining the necessary data transfer throughput through parallel channel operation.
3Area of stationary object
If buffer size is reduced to minimize area, then area occupancy decreases, but data transfer efficiency may be compromised
Solution Approach 1:
The patent resolves this contradiction by segmenting the buffer system into multiple channels, where each channel has its own smaller buffer. This segmentation ensures that data transfer efficiency is maintained through parallel processing across channels, while the total buffer area is reduced because each individual buffer only needs to handle a portion of the overall data load.
Solution Approach 2:
The patent combines multiple smaller channel buffers into a coordinated multi-channel system that collectively provides the necessary data transfer efficiency. By merging the capabilities of multiple small buffers working in parallel, the system achieves both reduced total area and maintained transfer efficiency, as the combined throughput of all channels matches or exceeds that of a single large buffer.
Data Source
AI summary
A first write data and a second write data destined for a first solid state storage channel and a second solid state storage channel, respectively, is received. The first write data is chopped using a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel. The second write data is chopped using the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel.