NAND Buffer Reuse for DRAM-Less MLC Programming

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Solution Overview

Problem

Multilevel cell nonvolatile memory programming requires volatile memory for caching, which increases cost and is not scalable, and using the host memory bus for caching results in performance penalties and infeasible garbage collection during low power states.

Innovation Solution

Implementing an internal buffer on the same die as the nonvolatile media, utilizing existing volatile memory for caching and programming, eliminating the need for external volatile memory and avoiding performance impacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If external volatile memory (DRAM) is added for caching programming data, then programming capability is improved, but cost and die area increase significantly

Engineering Contradiction:

Improveprogramming capabilityVSAvoiddie area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the volatile buffer functionality into the existing NAND die by utilizing the internal buffer structure that is already present in the NAND flash memory device. This eliminates the need for separate external DRAM chips while maintaining the caching capability required for multilevel cell programming, thereby improving integration and reducing overall die area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The internal buffer of the NAND die is made multi-functional by using it for both its original purpose (temporary data storage during NAND operations) and as a volatile cache for programming multilevel cells. This eliminates the need for dedicated external volatile memory, reducing cost and die area while maintaining programming capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If host memory bus is used for caching, then volatile memory capacity is improved, but performance deteriorates due to bandwidth sharing

Engineering Contradiction:

Improvevolatile memory capacityVSAvoidperformance

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent extracts the caching function from the host memory bus and relocates it to the NAND die itself. By using the internal buffer on the NAND die for volatile caching, the system eliminates the need to share the host memory bus bandwidth for caching operations, thereby maintaining full host bus bandwidth for actual data transfers while providing sufficient volatile cache capacity for programming operations.

Inventive Principle:

Principle #2Taking out (Extraction)

3Quantity of substance

If external volatile memory is added, then programming buffer capacity is improved, but device complexity increases

Engineering Contradiction:

Improvebuffer capacityVSAvoiddevice complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent combines the volatile buffer and NAND storage into a single integrated device. The internal buffer structure of the NAND flash is utilized for volatile caching, eliminating the need for separate external volatile memory components and their associated control logic, thereby maintaining buffer capacity while reducing overall device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentEP4020220B1Utilizing NAND buffer for dram-less multilevel cell programming

Publication Date: 2026.03.18 SK HYNIX NAND PRODUCT SOLUTIONS CORP

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AI summary

Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.