NAND Output Buffer Switching for Predictable ECC Read Latency
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Solution Overview
Problem
As NAND memory chips age, the increasing number of error correction bits leads to unpredictable performance degradation, affecting the time required to read and correct data, which is a concern for system designers aiming to maintain consistent performance.
Innovation Solution
An output buffer circuit with an error check circuit, an error correction circuit, and multiple storage circuits with switchable MUXs, allowing data to be stored and corrected efficiently across multiple buffers, ensuring consistent output at every clock cycle despite ECC degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on aged NAND memory with increasing error bits, then data reliability is maintained, but read time increases non-linearly from 0.5 usec to 10 usec
Solution Approach 1:
The patent performs error correction in advance by storing corrected data in a buffer before it is needed. The error correction circuit corrects data from aged NAND memory and stores the corrected data in a buffer, so when data is requested, the corrected data is already available, eliminating the need to wait for correction during read operations.
Solution Approach 2:
The patent divides the error correction process into separate stages: reading raw data from NAND memory, performing error correction in parallel, and storing corrected data in buffers. This segmentation allows error correction to occur independently and in advance of data requests, preventing time delays during actual reads.
2Reliability
If ECC bits are increased to correct more errors in aged memory, then error correction capability improves, but performance predictability deteriorates
Solution Approach 1:
By performing error correction in advance and storing corrected data in buffers, the system establishes predictable performance characteristics. The error correction process completes before data is needed, making read times consistent and predictable regardless of the number of ECC bits or memory age.
Solution Approach 2:
The patent introduces a buffer as an intermediary between the NAND memory and the data output. This buffer stores pre-corrected data, decoupling the error correction process from data requests and ensuring predictable performance by always serving corrected data without additional correction delays.
3Productivity
If multiple storage buffers are used to maintain consistent output, then performance consistency improves, but device complexity increases
Solution Approach 1:
The patent uses multiple storage buffers segmented into different states (empty, receiving raw data, receiving corrected data, ready for output). This segmentation allows parallel processing of multiple data items through different correction stages simultaneously, maintaining performance consistency without requiring complex coordination for single-item processing.
Solution Approach 2:
The patent implements a periodic state machine that cycles through buffer states in a predictable sequence. This periodic action simplifies control logic by using state transitions rather than complex conditional logic, managing multiple buffers systematically to maintain performance consistency.
Data Source
AI summary
An output buffer circuit for a non-volatile memory comprises an error check circuit, an error correction circuit, a switch circuit, and three storage circuits. The error check circuit receives the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected and generates a correction signal. The error correction circuit receives the plurality of data bits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. A switch enables the output buffer circuit to concurrently performs operations of error check, error correction, and transfer of data bits out of the output buffer circuit on three distinct pluralities of data bits. The switch allows reallocation of storage circuits to different operations without any data transfer.