Non-linear Buffer Offsets for Parallel NAND Write Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In managed NAND memory systems, the bandwidth and speed of sequential write operations are hindered by the need for large buffers to stage data, leading to decreased efficiency and increased power consumption.
Innovation Solution
Implementing a smaller buffer that uses non-linear or interleaved offsets for ready to transfer (RTT) commands, allowing data to be staged and programmed across multiple memory devices in parallel, thereby reducing storage space and improving transfer speed and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large buffers are used to stage data for sequential write operations, then data storage capacity is sufficient, but bandwidth and speed of write operations are hindered
Solution Approach 1:
The patent segments data into multiple smaller buffers instead of using one large buffer. Each buffer holds a portion of the data and can be independently processed and written to memory devices. This segmentation allows parallel write operations to proceed simultaneously from multiple buffers, increasing overall write speed while reducing the need for a single large buffer that would bottleneck the operation.
2Quantity of substance
If large buffers are used to stage data, then data can be staged for writing, but power consumption increases
Solution Approach 1:
By dividing the data into multiple smaller buffers, the system can process and write data in parallel from multiple buffers simultaneously. This reduces the time data spends in buffer staging, thereby reducing power consumption. Additionally, smaller buffers require less power to manage compared to a single large buffer system.
Solution Approach 2:
The patent enables continuous write operations by having multiple buffers ready to be written to memory devices in parallel. This eliminates idle time and waiting periods that would occur with a single large buffer, maintaining useful action continuously and reducing overall power consumption.
3Ease of operation
If data is staged in a buffer before writing, then write operations can be performed, but transfer speed is decreased
Solution Approach 1:
The patent uses multiple small buffers instead of one large buffer, allowing parallel write operations to proceed simultaneously from different buffers. This segmentation eliminates the bottleneck that would occur with a single buffer, maintaining ease of operation while significantly improving data transfer speed.
Solution Approach 2:
The patent transitions from a single-dimensional sequential buffer approach to a multi-dimensional parallel buffer approach. By organizing data across multiple buffers that can be processed simultaneously, the system adds a parallelism dimension that improves transfer speed while maintaining operational capability.
Data Source
AI summary
Methods, systems, and devices for techniques to perform a write operation are described. In response to receiving a sequential write command from a host system, the memory system may determine non-linear offsets for a set of requests for portions of the data. The memory system may determine a first subset of the data that includes data segments having logical addresses with gaps corresponding to the offset between the data segments to store in a first memory device. The memory system may store the first subset in a buffer and program the first subset to the first memory device. Additionally, the memory system may determine a second subset of data that using the offset and may transmit a second set of requests for the second subset of data, which may be stored in the buffer and programmed to a second memory device.