NAND Cache Programming Recovery via Page Buffer Release Protocols

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Solution Overview

Problem

In high-speed storage systems using NAND flash memory, the data-in time in page buffers limits overall system write performance due to prolonged programming and verification of multiple bits per memory cell, necessitating optimization of cache programming to prevent data loss and improve efficiency.

Innovation Solution

A method for controlling cache programming in NAND flash memory involves sending a programming failure signal to a memory controller, which initiates commands to release and reconstruct cached data, optimizing data handling through page buffer release and re-programming operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cache programming is implemented to reduce data-in time, then programming efficiency is improved, but data loss risk increases due to cache programming failure

Engineering Contradiction:

Improveprogramming efficiencyVSAvoiddata loss risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent loads new programming data into the page buffer in advance before the current programming operation completes. This preliminary action allows the system to prepare subsequent data during ongoing programming, reducing overall data-in time while maintaining data safety through the two-command release mechanism that prevents premature data loss

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies different release conditions to different data in the page buffer. New programming data is released only after successful completion of current programming, while current programming data is released after verification. This differentiated quality control resolves the contradiction by allowing aggressive optimization for new data while preserving reliability for critical current data

Inventive Principle:

Principle #3Local quality

2Loss of time

If new programming data is loaded into page buffer during ongoing programming, then data-in time is reduced, but page buffer management complexity increases

Engineering Contradiction:

Improvedata-in timeVSAvoidpage buffer management complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses the page buffer status indicator to provide feedback about the current state of the page buffer. This feedback mechanism allows the memory controller to make informed decisions about when to load new data and when to release cached data, simplifying the management complexity by providing clear state information without requiring complex tracking logic

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces a page buffer status indicator as an intermediary between the page buffer and the memory controller. This intermediary simplifies the interface by providing a clear status signal that mediates the complex interactions between data loading, programming operations, and data release, reducing management complexity while enabling efficient cache programming

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If verification is performed at multiple states during programming, then programming reliability is improved, but programming duration is prolonged

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogramming duration

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent performs verification at multiple states (intermediate verification states) during the programming process. This partial verification approach catches programming failures early at different verification states, improving reliability by detecting issues before complete programming while managing duration by stopping verification upon failure detection rather than completing all verification steps

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentEP4457644B1Interface protocols between memory controller and NAND flash memory for cache programming

Publication Date: 2026.04.01 YANGTZE MEMORY TECH CO LTD

Figure 1A
Figure 1B~1C
Figure 2A

AI summary

A method for controlling cache programming of a NAND flash memory is disclosed. A programming failure signal is received by a memory controller from the NAND flash memory indicative of failure of the cache programming. After receiving the programming failure signal, a first page buffer release command is sent by the memory controller to the NAND flash memory to release new programming data cached by the NAND flash memory. The cached new programming data is received by the memory controller from the NAND flash memory. After receiving the cached new programming data, a second page buffer release command is sent by the memory controller to the NAND flash memory to release current programming data used for the cache programming. The current programming data is received by the memory controller from the NAND flash memory. The current programming data is reconstructed by the NAND flash memory after releasing the cached new programming data.