NAND Flash Cache Latch Programming for Shorter Page Writes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices, particularly NAND Flash memory devices, face significant challenges in reducing the typical page programming time (tPROG), which is crucial for write performance, especially in single-level cell (SLC) and quad-level cell (QLC) NAND Flash memory devices, due to lengthy preparation times and overheads.
Innovation Solution
A cache program command is introduced to prepare the next program data and information during the current program operation and recovery operation, allowing simultaneous processing to reduce the total tPROG time by caching and preparing the next data and information during the ongoing operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the memory device waits for complete preparation of program data and information before each program operation, then the programming accuracy is ensured, but the page programming time (tPROG) increases significantly
Solution Approach 1:
The patent applies preliminary action by preparing program data and program information in advance during the recovery operation of previous programming tasks. The control logic caches next program data and determines next program information (including voltages and addresses) before they are actually needed, so that when a program operation starts, everything is ready immediately, eliminating waiting time while ensuring accuracy.
Solution Approach 2:
The patent implements continuity of useful action by overlapping the recovery operation with the preparation of subsequent program data and information. While the memory device is recovering from the first program operation, the control logic simultaneously caches the second program data and determines the second program information, ensuring that no time is wasted and the system continuously performs useful work without idle periods.
2Reliability
If the memory device processes program operations sequentially without overlap, then the programming quality is maintained, but the write performance and productivity decrease
Solution Approach 1:
The control logic performs preliminary actions by caching next program data and determining next program information during the recovery phase of current programming operations. This ensures that when the next program operation is needed, all preparations are already complete, maintaining quality while enabling faster sequential processing and improving overall write performance.
Solution Approach 2:
The patent enables continuous useful action by overlapping recovery operations with preparation operations. The memory device recovers from the first program operation while the control logic simultaneously prepares the second program data and information, eliminating idle time and improving productivity without compromising programming quality through the maintained preparation standards.
3Speed
If the memory device uses cache memory to temporarily store program data, then the programming speed is improved, but the device complexity increases
Solution Approach 1:
The control logic uses cache memory to store next program data and next program information in advance during recovery operations. This preliminary caching action enables faster access during subsequent program operations, improving programming speed. The complexity is managed by integrating this caching function within the existing control logic structure rather than adding separate complex systems.
Data Source
AI summary
In certain aspects, a method for programming a memory device includes caching first program data and preparing first program information, performing a first program operation using the first program data and the first program information, during the first program operation, caching a second program data in a first cache latch and preparing second program information, and after the first program operation is completed, performing a second program operation using the second program data and the second program information.